A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.

非二进制SAR ADC的电容失配校正方法

研究13比特逐次逼近型模数转换器的电容失配问题,提出结合DEM技术的基于LMS算法的校正方法。分析电容失配对权重的影响,为减小高精度ADC的面积开销,采用冗余结构的分段电容阵列,降低对电容失配的要求,为校正提供条件,设计基于LMS算法的结合DEM技术的校正方法。在MATLAB中搭建模型进行仿真,仿真结果表明,采用校正方法后INL可以达到-1.36/1.26LSB。

Design of digital calibration based on variable step size of sub-binary SAR ADC

Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.

基于建立-向下偏转过程11-bit 1-MS/s逐次逼近型模数转换器的设计

采用0.35μm CMOS工艺设计了一款基于建立-向下(set-and-down)偏转过程11-bit1-MS/s的逐次逼近型模数转换器(SAR ADC),分析了电容网络的偏转过程。采用本文电容偏转过程的11-bit SAR ADC平均电容偏转能耗比传统的SAR ADC降低了81.25%,且单位电容的总数与传统SAR ADC相比也降低了50%。采用0.35μm 2P3M CMOS工艺对SARADC电路进行了版图绘制,版图尺寸约为705μm×412μm。后仿真结果表明,信号与噪声和失真比达到了66.6dB,有效精度达到了10.7bit。

Fully-Differential Multichannel Integrated Neural Signal Recording Front-End

Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-channel fully-differential neural recording chip is designed.The chip consists of 16-channel low-noise pre-amplifiers,a multiplexer and a successive approximation register（SAR）ADC.The result shows that the equivalent input-referred noise of recording amplifier is 3.63μV,bringing down noise efficiency factor to 4.24.At 8.5 bits effective number of bit（ENOB）,the analog-to-digital converter（ADC）has an SNR of 52.6dB.The core area of the proposed neural recording front-end is about 2.46 mm^2.

A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fastsettling routing in high speed SAR ADCs

Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pacitor size. In this paper, a small size three-dimensional （3-D） metal-oxide-metal （MOM） capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that 1NL is less than -4-1 LSB and DNL is less than ＋0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.

A low power 11-bit 100 MS/s SAR ADC IP

This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IR Each channel adopts flash- SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it to asynchronously trigger the comparator in the fine SAR ADC in high speed. MOM capacitors with a fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55 nm low leakage CMOS technology and the active area of dual-channel （I-Q） ADC is 0.35 mm2, while the core area is 0.046 mm2. It consumes 2.92 mA at a 1.2 V supply, for dual-channel too. The effective number of bits （ENOB） is 9.90 bits at 2.4 MHz input frequency, and 9.34 bits at 50 MHz, leading to a FOM of 18.3 fJ/conversion-step.

An 11-bit ENOB,accuracy-programmable,and non-calibrating time-mode SAR ADC

A 10 or 12 bit programmable successive approximation register（SAR） ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio（SNDR） of 68 dB（11 ENOB）,a spurious free dynamic range（SFDR） of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.

An 8-b 300MS/s folding and interpolating ADC for embedded applications

A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter（ADC） is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm^2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.