针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(T...针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(Time Amplifier,TA)成功实现了相位积累速度的指数级增加,有效减小了输入信号相位脱离鉴相器的“死区”所需的振荡周期数,缩短了比较延迟,优化了比较的速度和功耗。该比较器基于65 nm CMOS工艺进行设计,在0.4 V电源电压下功耗仅5.24 nW,失调电压为5.99 mV。展开更多
针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applicatio...This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applications. In order to improve the SAR-ADC＇s accuracy, a novel comparator is proposed in which the offset voltage is self- calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio （SINAD） of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 ×1080μm2.展开更多
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(Time Amplifier,TA)成功实现了相位积累速度的指数级增加,有效减小了输入信号相位脱离鉴相器的“死区”所需的振荡周期数,缩短了比较延迟,优化了比较的速度和功耗。该比较器基于65 nm CMOS工艺进行设计,在0.4 V电源电压下功耗仅5.24 nW,失调电压为5.99 mV。
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
基金supported by the Special-Funded Program on National Key Scientific Instruments and Equipment Development(No.2011YQ040082)
文摘This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applications. In order to improve the SAR-ADC＇s accuracy, a novel comparator is proposed in which the offset voltage is self- calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio （SINAD） of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 ×1080μm2.
