This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transac...This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.展开更多
参考服务器/客户端的可堆叠通信模式,以最常见的SATA硬盘作为存储介质,Marvell 88SM9705为核心控制芯片,设计了一种可堆叠的存储介质。经测试,88SM9705通过解析主机端发送来的SATA 3.0协议定义的帧信息结构(Frame Information Structure...参考服务器/客户端的可堆叠通信模式,以最常见的SATA硬盘作为存储介质,Marvell 88SM9705为核心控制芯片,设计了一种可堆叠的存储介质。经测试,88SM9705通过解析主机端发送来的SATA 3.0协议定义的帧信息结构(Frame Information Structure,FIS)中PM Port地址字段,能依次对其所连接的多个SATA硬盘进行正确的读、写等操作,实现了存储设备的可堆叠,稳定性能良好。是一种实现扩容同步提速的可堆叠存储阵列解决方案,在嵌入式存储系统领域具有很好的应用前景。展开更多
文摘This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.
