SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics...SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.展开更多
A simulation method to simulate the pseudorandom code P. M PP radar＇ s echo signal is proposed that makes use of the pre-generated Doppler simulation data, according to the relative movement parameter of the radar an...A simulation method to simulate the pseudorandom code P. M PP radar＇ s echo signal is proposed that makes use of the pre-generated Doppler simulation data, according to the relative movement parameter of the radar and the target. It resolves the problem of the high precision distance simulation and the high speed digital shift phase. At the same time, the radar dynamic digital video frequency target signal simulator is designed. Simulation results of the critical unit and the output waveform are given. The result of the test satisfies the system＇s request.展开更多
A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS...A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.展开更多
文摘SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.
文摘A simulation method to simulate the pseudorandom code P. M PP radar＇ s echo signal is proposed that makes use of the pre-generated Doppler simulation data, according to the relative movement parameter of the radar and the target. It resolves the problem of the high precision distance simulation and the high speed digital shift phase. At the same time, the radar dynamic digital video frequency target signal simulator is designed. Simulation results of the critical unit and the output waveform are given. The result of the test satisfies the system＇s request.
基金Project supported by the Major National Scientific Research Plan of China(No.2011 CB933202)the National High Technology Research and Development Program of China(No.2008AA010701)
文摘A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.
