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面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计
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作者 牛志强 陈志坤 +4 位作者 胡子阳 王刚 刘剑 吴南健 冯鹏 《集成电路与嵌入式系统》 2024年第5期48-54,共7页
针对高帧率CMOS图像传感器的应用需求,提出一种结合逐次逼近型(Successive Approximation Register,SAR)和单斜坡(Single Slope,SS)结构的混合型模拟数字转换器(Analog to Digital Converter,ADC)。该ADC的分辨率为12位,其中SAR ADC实现... 针对高帧率CMOS图像传感器的应用需求,提出一种结合逐次逼近型(Successive Approximation Register,SAR)和单斜坡(Single Slope,SS)结构的混合型模拟数字转换器(Analog to Digital Converter,ADC)。该ADC的分辨率为12位,其中SAR ADC实现高6位量化,SS ADC实现低6位量化。该ADC采用了全差分结构消除采样开关的固定失调并减少非线性误差,同时在SAR ADC中采用了异步逻辑电路进一步缩短转换周期。采用110 nm 1P4M CMOS工艺对该电路进行了设计和版图实现,后仿真结果表明,在20 MHz的时钟下,转换周期仅为3.3μs,无杂散动态范围为77.12 dB,信噪失真比为67.38 dB,有效位数为10.90位。 展开更多
关键词 高帧率cmos图像传感器 混合型列ADC 单斜ADC 逐次逼近型ADC 电流舵DAC
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不同能量质子辐照CMOS图像传感器的单粒子瞬态效应研究
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作者 李钰 文林 郭旗 《现代应用物理》 2024年第3期112-119,共8页
针对空间环境宽能谱质子辐射导致的CMOS图像传感器单粒子效应问题,开展了不同能量质子辐照试验,研究了质子辐照导致CMOS图像传感器单粒子效应的异常现象、图像特征及参数性能变化规律。试验表明,质子辐照主要导致CMOS图像传感器出现明... 针对空间环境宽能谱质子辐射导致的CMOS图像传感器单粒子效应问题,开展了不同能量质子辐照试验,研究了质子辐照导致CMOS图像传感器单粒子效应的异常现象、图像特征及参数性能变化规律。试验表明,质子辐照主要导致CMOS图像传感器出现明显的单粒子瞬态(single event transient,SET)效应现象,包括SET亮斑和亮线。通过对比不同条件下的试验结果,分析了质子能量、积分时间等变化对SET亮斑覆盖像素情况、信号水平的影响规律,并结合TCAD仿真工具,分析了SET亮斑的产生机制。研究结果表明:SET亮斑灰度水平和覆盖像素数目均随辐照质子能量增加而增大;SET亮斑覆盖像素最大灰度值、平均灰度值随CMOS图像传感器积分时间增加而增大,通过调节CMOS图像传感器的积分时间,可以明显改变SET亮斑的特征和器件成像性能;从TCAD软件仿真的微观物理过程获得了SET亮斑随积分时间变化的机制,支持了对试验结果的分析和判断。研究结果可为CMOS图像传感器空间辐射效应评估、抗辐射加固提供试验和理论参考。 展开更多
关键词 质子辐照 空间环境 cmos图像传感器 单粒子效应 瞬态效应
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Total ionizing dose effect modeling method for CMOS digital-integrated circuit
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作者 Bo Liang Jin-Hui Liu +3 位作者 Xiao-Peng Zhang Gang Liu Wen-Dan Tan Xin-Dan Zhang 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2024年第2期32-46,共15页
Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID eff... Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs. 展开更多
关键词 cmos digital-integrated circuit Total ionizing dose IBIS model Behavior-physical hybrid model Physical parameters
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A Hybrid Level Set Optimization Design Method of Functionally Graded Cellular Structures Considering Connectivity
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作者 Yan Dong Kang Zhao +1 位作者 Liang Gao Hao Li 《Computers, Materials & Continua》 SCIE EI 2024年第4期1-18,共18页
With the continuous advancement in topology optimization and additive manufacturing(AM)technology,the capability to fabricate functionally graded materials and intricate cellular structures with spatially varying micr... With the continuous advancement in topology optimization and additive manufacturing(AM)technology,the capability to fabricate functionally graded materials and intricate cellular structures with spatially varying microstructures has grown significantly.However,a critical challenge is encountered in the design of these structures–the absence of robust interface connections between adjacent microstructures,potentially resulting in diminished efficiency or macroscopic failure.A Hybrid Level Set Method(HLSM)is proposed,specifically designed to enhance connectivity among non-uniform microstructures,contributing to the design of functionally graded cellular structures.The HLSM introduces a pioneering algorithm for effectively blending heterogeneous microstructure interfaces.Initially,an interpolation algorithm is presented to construct transition microstructures seamlessly connected on both sides.Subsequently,the algorithm enables the morphing of non-uniform unit cells to seamlessly adapt to interconnected adjacent microstructures.The method,seamlessly integrated into a multi-scale topology optimization framework using the level set method,exhibits its efficacy through numerical examples,showcasing its prowess in optimizing 2D and 3D functionally graded materials(FGM)and multi-scale topology optimization.In essence,the pressing issue of interface connections in complex structure design is not only addressed but also a robust methodology is introduced,substantiated by numerical evidence,advancing optimization capabilities in the realm of functionally graded materials and cellular structures. 展开更多
关键词 hybrid level set method functionally graded cellular structure CONNECTIVITY interpolated transition optimization design
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一种SET的SPICE宏模型及SET/CMOS混合系统仿真研究
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作者 马彦芬 杨晓光 孙铁署 《河北大学学报(自然科学版)》 CAS 北大核心 2009年第1期95-98,共4页
基于单电子晶体管(SET)数学分析模型,改进了它的SPICE宏模型.该模型考虑了背景电荷的影响,由1个电压控制电流源、1个电压控制电压源构成.与准分析模型相比较,该模型准确地表现了SET的I-U特性.通过A/D转换器的仿真实例表明,所设计的3位SE... 基于单电子晶体管(SET)数学分析模型,改进了它的SPICE宏模型.该模型考虑了背景电荷的影响,由1个电压控制电流源、1个电压控制电压源构成.与准分析模型相比较,该模型准确地表现了SET的I-U特性.通过A/D转换器的仿真实例表明,所设计的3位SET/CMOS混合系统具有良好的适用性和精确度,可以推广到SET/CMOS混合系统的管子级设计. 展开更多
关键词 set SPICE宏模型 I-U特性 set/cmos混合系统 A/D
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一种SET/CMOS混合器件模型的建立及特性分析 被引量:1
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作者 史党院 蔡理 邵一丹 《微计算机信息》 北大核心 2007年第29期283-284,106,共3页
本文基于一种单电子晶体管数学模型(改进的MIB模型),实现其SPICE宏模型。提出一种改进型SET/CMOS混合器件模型,并用SPICE对其I-V特性进行了仿真验证,仿真结果证实了电流与电压具有线性关系。此混合模型的线性电流区可以在积分器以及滤... 本文基于一种单电子晶体管数学模型(改进的MIB模型),实现其SPICE宏模型。提出一种改进型SET/CMOS混合器件模型,并用SPICE对其I-V特性进行了仿真验证,仿真结果证实了电流与电压具有线性关系。此混合模型的线性电流区可以在积分器以及滤波器电路中得到应用。 展开更多
关键词 单电子晶体管 set/cmos 库伦阻塞效应 SPICE
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混合型CMOS-忆阻与非/或非单元的设计及应用
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作者 饶历 李路平 林弥 《杭州电子科技大学学报(自然科学版)》 2023年第2期13-18,共6页
针对级联型运算单元的延迟问题,设计了一种新的CMOS-忆阻与非/或非逻辑电路结构。首先,采用阈值型压控忆阻器模型,以忆阻器和CMOS晶体管为核心,设计了一款混合型CMOS-忆阻与非/或非逻辑运算单元,有效减小了延迟时间;然后,将混合型CMOS-... 针对级联型运算单元的延迟问题,设计了一种新的CMOS-忆阻与非/或非逻辑电路结构。首先,采用阈值型压控忆阻器模型,以忆阻器和CMOS晶体管为核心,设计了一款混合型CMOS-忆阻与非/或非逻辑运算单元,有效减小了延迟时间;然后,将混合型CMOS-忆阻与非/或非逻辑运算单元应用到了八线三线编码器电路的设计中,通过控制不同的输入信号能得到对应的二进制编码信号;最后,通过PSPICE仿真验证了设计电路的正确性。 展开更多
关键词 阈值型压控忆阻器 cmos-忆阻混合电路 与非/或非
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Hybrid Dynamic Variables-Dependent Event-Triggered Fuzzy Model Predictive Control 被引量:1
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作者 Xiongbo Wan Chaoling Zhang +2 位作者 Fan Wei Chuan-Ke Zhang Min Wu 《IEEE/CAA Journal of Automatica Sinica》 SCIE EI CSCD 2024年第3期723-733,共11页
This article focuses on dynamic event-triggered mechanism(DETM)-based model predictive control(MPC) for T-S fuzzy systems.A hybrid dynamic variables-dependent DETM is carefully devised,which includes a multiplicative ... This article focuses on dynamic event-triggered mechanism(DETM)-based model predictive control(MPC) for T-S fuzzy systems.A hybrid dynamic variables-dependent DETM is carefully devised,which includes a multiplicative dynamic variable and an additive dynamic variable.The addressed DETM-based fuzzy MPC issue is described as a “min-max” optimization problem(OP).To facilitate the co-design of the MPC controller and the weighting matrix of the DETM,an auxiliary OP is proposed based on a new Lyapunov function and a new robust positive invariant(RPI) set that contain the membership functions and the hybrid dynamic variables.A dynamic event-triggered fuzzy MPC algorithm is developed accordingly,whose recursive feasibility is analysed by employing the RPI set.With the designed controller,the involved fuzzy system is ensured to be asymptotically stable.Two examples show that the new DETM and DETM-based MPC algorithm have the advantages of reducing resource consumption while yielding the anticipated performance. 展开更多
关键词 Dynamic event-triggered mechanism(DETM) hybrid dynamic variables model predictive control(MPC) robust positive invariant(RPI)set T-S fuzzy systems
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异步控制set-C单元的三种CMOS实现
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作者 罗玲玉 杨银堂 +1 位作者 周端 徐阳扬 《微计算机信息》 北大核心 2008年第26期274-276,共3页
本文提出了由CMOS实现的带set置位端C单元电路(记为set-C单元)的三种不同实现方案,介绍了每种方案下的管级电路及工作原理。采用0.25um标准CMOS工艺的瞬态仿真验证了所提出设计方案的正确性。通过HSPICE仿真,给出了三种方案的能耗、上... 本文提出了由CMOS实现的带set置位端C单元电路(记为set-C单元)的三种不同实现方案,介绍了每种方案下的管级电路及工作原理。采用0.25um标准CMOS工艺的瞬态仿真验证了所提出设计方案的正确性。通过HSPICE仿真,给出了三种方案的能耗、上升延迟与下降延迟的对比曲线。仿真结果表明,方案一较方案二的节能可达46%,较方案三的节能可达13%,由此得出方案一较佳的结论。 展开更多
关键词 异步控制 set-C单元 cmos实现 仿真 能耗 延时
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Attribute Reduction of Hybrid Decision Information Systems Based on Fuzzy Conditional Information Entropy
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作者 Xiaoqin Ma Jun Wang +1 位作者 Wenchang Yu Qinli Zhang 《Computers, Materials & Continua》 SCIE EI 2024年第5期2063-2083,共21页
The presence of numerous uncertainties in hybrid decision information systems(HDISs)renders attribute reduction a formidable task.Currently available attribute reduction algorithms,including those based on Pawlak attr... The presence of numerous uncertainties in hybrid decision information systems(HDISs)renders attribute reduction a formidable task.Currently available attribute reduction algorithms,including those based on Pawlak attribute importance,Skowron discernibility matrix,and information entropy,struggle to effectively manages multiple uncertainties simultaneously in HDISs like the precise measurement of disparities between nominal attribute values,and attributes with fuzzy boundaries and abnormal values.In order to address the aforementioned issues,this paper delves into the study of attribute reduction withinHDISs.First of all,a novel metric based on the decision attribute is introduced to solve the problem of accurately measuring the differences between nominal attribute values.The newly introduced distance metric has been christened the supervised distance that can effectively quantify the differences between the nominal attribute values.Then,based on the newly developed metric,a novel fuzzy relationship is defined from the perspective of“feedback on parity of attribute values to attribute sets”.This new fuzzy relationship serves as a valuable tool in addressing the challenges posed by abnormal attribute values.Furthermore,leveraging the newly introduced fuzzy relationship,the fuzzy conditional information entropy is defined as a solution to the challenges posed by fuzzy attributes.It effectively quantifies the uncertainty associated with fuzzy attribute values,thereby providing a robust framework for handling fuzzy information in hybrid information systems.Finally,an algorithm for attribute reduction utilizing the fuzzy conditional information entropy is presented.The experimental results on 12 datasets show that the average reduction rate of our algorithm reaches 84.04%,and the classification accuracy is improved by 3.91%compared to the original dataset,and by an average of 11.25%compared to the other 9 state-of-the-art reduction algorithms.The comprehensive analysis of these research results clearly indicates that our algorithm is highly effective in managing the intricate uncertainties inherent in hybrid data. 展开更多
关键词 hybrid decision information systems fuzzy conditional information entropy attribute reduction fuzzy relationship rough set theory(RST)
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基于混合忆阻器-CMOS逻辑的全加器电路优化设计 被引量:5
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作者 冯朝文 蔡理 +2 位作者 杨晓阔 张波 危波 《微纳电子技术》 北大核心 2019年第11期868-874,894,共8页
将一种电压阈值型压控双极性忆阻器模型与CMOS反相器进行混合设计,实现了"与"、"或"、"与非"、"或非"基本逻辑门。通过构建"异或"逻辑门新结构,提出一种基于混合忆阻器-CMOS逻辑的... 将一种电压阈值型压控双极性忆阻器模型与CMOS反相器进行混合设计,实现了"与"、"或"、"与非"、"或非"基本逻辑门。通过构建"异或"逻辑门新结构,提出一种基于混合忆阻器-CMOS逻辑的全加器电路优化设计方案。最后,分析忆阻器参数β,Vt,Ron和Roff对电路运算速度和输出信号衰减幅度的影响,研究了该优化设计的电路功能和特性,经验证模拟仿真结果与理论分析结果具有较好的一致性。研究结果表明:全加器优化设计结构更简单,版图面积更小,所需忆阻器数量减少22.2%,CMOS反相器数量减少50%;增大参数β值可提高运算速度,增大忆阻值比率Roff/Ron可减小逻辑输出信号衰减度。 展开更多
关键词 忆阻器 混合忆阻器-cmos逻辑 电压阈值 全加器 信号衰减
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纳米/CMOS电路单元的快速映射 被引量:1
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作者 储著飞 夏银水 王伦耀 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2011年第3期514-520,共7页
针对纳米/CMOS混合电路(CMOL)单元映射问题,提出一种基于混合遗传算法的映射算法.将任意布尔电路转换为适于CMOL映射的基于或非门的电路,读入该电路进行染色体编码,形成初始种群;每一代种群经过二维交叉算子、变异算子进行解空间全局搜... 针对纳米/CMOS混合电路(CMOL)单元映射问题,提出一种基于混合遗传算法的映射算法.将任意布尔电路转换为适于CMOL映射的基于或非门的电路,读入该电路进行染色体编码,形成初始种群;每一代种群经过二维交叉算子、变异算子进行解空间全局搜索,并引入模拟退火算法进行局部搜索使种群个体得以改进.对ISCAS和MCNC标准电路的实验结果表明,采用该算法进行求解不仅使电路面积小、时延短,且具有求解速度快、能处理规模较大电路的特点. 展开更多
关键词 纳米混合电路 映射 混合遗传算法 优化
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深亚微米CMOS反相器的单粒子瞬态效应研究 被引量:2
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作者 高成 张芮 +1 位作者 王怡豪 黄姣英 《微电子学》 CAS 北大核心 2019年第5期729-734,共6页
针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值... 针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。 展开更多
关键词 cmos反相器 单粒子瞬态效应 TCAD仿真 脉冲激光试验
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混合忆阻器-CMOS逻辑运算的优化设计研究 被引量:2
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作者 冯朝文 白鹏 +1 位作者 杨晓阔 危波 《计算机技术与发展》 2019年第12期44-48,54,共6页
基于混合忆阻器-CMOS设计成的典型逻辑门在输出端的忆阻器存在泄露电流,导致运算输出信号幅度产生衰减,引起多级互联电路逻辑运算混乱甚至出错。为了解决这一难题,文中提出采用变形逻辑运算表达式,以CMOS反相器可实现的“非”逻辑操作... 基于混合忆阻器-CMOS设计成的典型逻辑门在输出端的忆阻器存在泄露电流,导致运算输出信号幅度产生衰减,引起多级互联电路逻辑运算混乱甚至出错。为了解决这一难题,文中提出采用变形逻辑运算表达式,以CMOS反相器可实现的“非”逻辑操作完成输出端信号传递这一方案,改进了电路运算设计结构但不改变电路运算的复杂度。进而以“异或”、“异或非”逻辑门和一位全加器为例,以理论分析、新电路结构设计和PSpice软件模拟仿真三者共同验证了该方案的有效性。研究结果表明,该方案很好地解决了级间连接忆阻器的泄露电流,有效降低了逻辑运算信号的衰减现象,且改进设计的电路逻辑功能正确,运算准确性得到提高,输出信号低电平近似为0 V,高电平达1.8 V,均接近理想值,有利于实现新型高性能复杂逻辑运算的设计、开发和大规模集成应用。 展开更多
关键词 混合忆阻器-cmos 逻辑门 信号衰减 全加器 暂态响应
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Effect of Enhanced UV-B Radiation on Seed Setting Rate and 1 000-grain Weight of Indica Hybrid Rice Restorer Lines
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作者 况浩池 曾祥瑞 +5 位作者 罗俊涛 曾正明 杨扬 陈光珍 何兴材 付均 《Agricultural Science & Technology》 CAS 2013年第2期226-229,共4页
[Objective] This study was to investigate the effect of enhanced UV-B radiation on seed setting rate and 1 000-grain weight of hybrid rice combinations. [Method] The seed setting rate and 1 000-grain weight of 10 new ... [Objective] This study was to investigate the effect of enhanced UV-B radiation on seed setting rate and 1 000-grain weight of hybrid rice combinations. [Method] The seed setting rate and 1 000-grain weight of 10 new sterile indica restorer lines planted in pots under enhanced UV-B radiation and fluorescent lamps (control) were respectively measured, and the differences were compared. [Result] The enhanced UV-B radiation significantly reduced the seed setting rate of indica restorer lines, and the differences between that UV-B radiation treatment and control all reached extremely significant level. In addition, the enhanced UV-B radiation reduced the 1 000-grain weight of most indica restorer lines, and compared with that of control the difference achieved significant or very significant level. However, the effect of enhanced UV-B radiation on seed setting rate and 1 000-grain weight differed to different indica restorer lines, and the differences among restorer lines tested were significant or very significant, which indicated the possibility to screen antiUV-B radiation rice materials and combinations. Finally, the indica restorer lines 09R-14, Luhui 37 and 10R-7703 which were strongly resistant to UV-B radiation were screened out. [Conclusion] This study laid foundation for breeding hybrid rice varieties resistance to UV-B radiation. 展开更多
关键词 UV-B radiation Indica restorer lines hybrid rice Seed setting rate Grain weight
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64×64元InSb阵列CMOS读出电路
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作者 刘昌林 李仁豪 《半导体光电》 CAS CSCD 北大核心 2000年第A03期53-55,共3页
根据 6 4× 6 4元InSb红外探测器对读出电路的要求 ,运用电路模拟和CAD技术 ,设计并研制了以X -Y寻址方式的 6 4× 6 4元InSb红外探测器用信号读出电路。文章重点介绍了6 4× 6 4元InSb阵列CMOS读出电路的工作原理和设计考虑。
关键词 读出电路 cmos 红外探测器 锑化铟
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CMOS中断在系统定时上的应用 被引量:1
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作者 刘春旭 薛连发 《黑龙江大学自然科学学报》 CAS 1997年第4期40-41,共2页
分析了CMOS实时时钟系统在系统定时上的应用。
关键词 cmos 中断 定时 实时时钟系统 软件设计
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Studies on Seed Setting Stability in Associated with Temperature for a Two-Line Hybrid Rice,Liangyoupeijiu 被引量:7
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作者 LuChuan-gen ZONGShou-yu ZOUJiang-shi 《Rice science》 SCIE 2004年第4期191-194,共4页
When being planted in wide areas in southern China (23°23' - 33°23' N, 98°35' - 120°19' E, sea level above 2.7 - 1285 m), Liangyoupeijiu (LYPJ), a two-line hybrid rice combination, ... When being planted in wide areas in southern China (23°23' - 33°23' N, 98°35' - 120°19' E, sea level above 2.7 - 1285 m), Liangyoupeijiu (LYPJ), a two-line hybrid rice combination, showed a seed setting rate of 75.2 - 77.2%, which was lower by 4.3 - 7.5 percent point than that of an indica hybrid rice Shanyou 63 (CK), with similar values of grain yield and coefficients of variation to CK. Sowing during 5-25th of May in Nanjing (32°3' N, 118°48' E), China, LYPJ headed before 4th September, and gave a seed setting rate of 75 - 90%, and grain yield over 1 kg/m2. If the sowing date was delayed to 14 - 15th, June, its heading date would be as late as 17th - 21st September, and seed setting rate would be declined by 10 - 15% in comparison with that on a suitable sowing date. When flowering took place at an average daily temperature range of 13.7 - 28.5℃ for five days, the spikelet fertility (SF) would be increased by 1.9- 10.7%, for each increment of 1℃. The suitable (SF≥90%) and safe (SF≥75%) temperatures for flowering stage were indicated to be 26.5℃ and 22.9℃, respectively. To get a high and stable seed set in cultivating LYPJ, it was recommended that LYPJ would be planted in the areas south of 34癗, and the favorable average daily temperature during flowering stage should be at 26 - 28℃. 展开更多
关键词 RICE intersubspecific hybrid seed setting rate grain yield TEMPERATURE
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基于R-HBT模型的三值CMOS忆阻混合型D触发器 被引量:1
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作者 韩琪 王旭亮 +2 位作者 吴巧 罗文瑶 林弥 《杭州电子科技大学学报(自然科学版)》 2021年第6期1-5,共5页
研究多值忆阻逻辑电路,采用三值忆阻逻辑运算单元,设计了三值CMOS忆阻混合型D锁存器,该三值忆阻逻辑运算单元以CMOS和电阻异质结双极性晶体管(Resistor-Heterojunction Bipolar Transistor,R-HBT)负阻型忆阻器等效模型为核心,构成的三值... 研究多值忆阻逻辑电路,采用三值忆阻逻辑运算单元,设计了三值CMOS忆阻混合型D锁存器,该三值忆阻逻辑运算单元以CMOS和电阻异质结双极性晶体管(Resistor-Heterojunction Bipolar Transistor,R-HBT)负阻型忆阻器等效模型为核心,构成的三值CMOS忆阻混合型D锁存器包括4个三值忆阻与非单元和1个三值忆阻反相器,结构简单。在忆阻D锁存器的基础上,设计了上边沿触发的三值CMOS忆阻混合型D触发器,该D触发器为主从型结构。PSPICE仿真结果符合三值D触发器的逻辑功能,验证了设计的正确性。 展开更多
关键词 忆阻器 cmos混合型 多值逻辑 D触发器
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BIOS刷新、BIOS设置与CMOS设置 被引量:2
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作者 俞凯 《重庆科技学院学报(自然科学版)》 CAS 2008年第2期127-128,共2页
介绍BIOS刷新、BIOS与CMOS设置的概念及异同,以AWARD BIOS为例介绍CMOS中各项参数设置的意义。
关键词 cmos设置 BIOS设置 BIOS刷新 参数设置
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