A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the...A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.展开更多
An 8-b 100-MS/s pipelined analog-to-digital converter（ADC） is presented.Without the dedicated sample-and -hold amplifier（SHA）,it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the ...An 8-b 100-MS/s pipelined analog-to-digital converter（ADC） is presented.Without the dedicated sample-and -hold amplifier（SHA）,it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the effective number of bits is 7.43 bit and 6.94 bit for 1-MHz and 80-MHz input signal,respectively,at 100 MS/s.The power dissipation is 23.4 mW including voltage/current reference at 1.8-V supply,and FoM is 0.85 pJ/step.The ADC core area is 0.53 mm^2.INL is -0.99 to 0.76 LSB,and DNL is -0.49 to 0.56 LSB.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011607)the State Key Laboratory of China
文摘A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011600)the Young Scientists Fund of Fudan University,China(No.09FQ33)the State Key Laboratory of ASIC & System(Fudan University),China (No.09MS008).
文摘An 8-b 100-MS/s pipelined analog-to-digital converter（ADC） is presented.Without the dedicated sample-and -hold amplifier（SHA）,it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the effective number of bits is 7.43 bit and 6.94 bit for 1-MHz and 80-MHz input signal,respectively,at 100 MS/s.The power dissipation is 23.4 mW including voltage/current reference at 1.8-V supply,and FoM is 0.85 pJ/step.The ADC core area is 0.53 mm^2.INL is -0.99 to 0.76 LSB,and DNL is -0.49 to 0.56 LSB.
