In this article,we comment on the article by Huang et al.The urgent development of new therapeutic strategies targeting macrophage polarization is critical in the fight against liver cancer.Tumor-associated macrophage...In this article,we comment on the article by Huang et al.The urgent development of new therapeutic strategies targeting macrophage polarization is critical in the fight against liver cancer.Tumor-associated macrophages(TAMs),primarily of the M2 subtype,are instrumental in cellular communication within the tumor microenvironment and are influenced by various signaling pathways,including the wingless/integrated(Wnt)pathway.Activation of the Wnt signaling pathway is pivotal in promoting M2 TAMs polarization,which in turn can exacerbate hepatocarcinoma cell proliferation and migration.This manuscript emphasizes the burgeoning significance of the Wnt signaling pathway and M2 TAMs polarization in the pathogenesis and progression of liver cancer,highlighting the potential therapeutic benefits of inhibiting the Wnt pathway.Lastly,we point out areas in Huang et al’s study that require further research,providing guidance and new directions for similar studies.展开更多
The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
The device is used for the test on the fuze detonating time according to the initial velocity of the projectile and the altitude and speed of enemy aircraft flight. For the special requirements of the high-speed signa...The device is used for the test on the fuze detonating time according to the initial velocity of the projectile and the altitude and speed of enemy aircraft flight. For the special requirements of the high-speed signal acquisition in the process, the characteristics of the measured signal are analyzed. The system is investigated in chip selection, signal transmission, signal processing, signal storage, post-production PCB design, etc. The appropriate measures and solutions which affect the integrity and accuracy of the signal in each process are proposed. The rules for the layout of the device and wiring are made. The result show that the measurement values are accurate without loss of data.展开更多
Silicon(Si)diffraction microlens arrays are usually used to integrating with infrared focal plane arrays(IRFPAs)to improve their performance.The errors of lithography are unavoidable in the process of the Si diffrac-t...Silicon(Si)diffraction microlens arrays are usually used to integrating with infrared focal plane arrays(IRFPAs)to improve their performance.The errors of lithography are unavoidable in the process of the Si diffrac-tion microlens arrays preparation in the conventional engraving method.It has a serious impact on its performance and subsequent applications.In response to the problem of errors of Si diffraction microlens arrays in the conven-tional method,a novel self-alignment method for high precision Si diffraction microlens arrays preparation is pro-posed.The accuracy of the Si diffractive microlens arrays preparation is determined by the accuracy of the first li-thography mask in the novel self-alignment method.In the subsequent etching,the etched area will be protected by the mask layer and the sacrifice layer or the protective layer.The unprotection area is carved to effectively block the non-etching areas,accurately etch the etching area required,and solve the problem of errors.The high precision Si diffraction microlens arrays are obtained by the novel self-alignment method and the diffraction effi-ciency could reach 92.6%.After integrating with IRFPAs,the average blackbody responsity increased by 8.3%,and the average blackbody detectivity increased by 10.3%.It indicates that the Si diffraction microlens arrays can improve the filling factor and reduce crosstalk of IRFPAs through convergence,thereby improving the perfor-mance of the IRFPAs.The results are of great reference significance for improving their performance through opti-mizing the preparation level of micro nano devices.展开更多
The elaborate redox network of the cell,comprising of events like turnover of reactive oxygen species(ROS),redox sensing,signaling,expression of redox-sensitive genes,etc.,often orchestrates with other bonafide hormon...The elaborate redox network of the cell,comprising of events like turnover of reactive oxygen species(ROS),redox sensing,signaling,expression of redox-sensitive genes,etc.,often orchestrates with other bonafide hormonal signaling pathways through their synergistic or antagonistic action in the plant cell.The redox cue generated in plant cells under fluctuating environmental conditions can significantly influence other hormonal biosynthetic or signaling mechanisms,thereby modulating physiology towards stress acclimation and defense.There is also strong evidence of the recruitment of ROS as a‘second messenger’in different hormonal signaling pathways under stress.Moreover,the retrograde signaling initiated by ROS also found to strongly influence hormonal homeostasis and signaling.The present review,in this aspect,is an effort towards understanding the regulatory roles of ROS in integrating and orchestrating other hormonal signaling pathways or vice versa so as to unfold the relationship between these two signaling episodes of plant cells under environmental odds.We also accentuate the significance of understanding the utterly complex interactions,which occur both at metabolic and genetic levels between ROS and phytohormones during stress combinations.Furthermore,the significant and decisive role of ROS turnover,particularly the contribution of RBOH(respiratory burst oxidase homologs)in the synergism of redox and hormone signaling during systemic acquired acclimation under stress is also discussed.展开更多
---Double data rate synchronous dynamic random access memory (DDR3) has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integri...---Double data rate synchronous dynamic random access memory (DDR3) has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integrity (SI) simulation flow for the DDR3 interface, two system-level SI simulation methodologies, which are board-level S-parameter extraction in the frequency-domain and system-level simulation assumptions in the time domain, are introduced in this paper. By comparing the flow of Speed2000 and PowerSI/Hspice, PowerSI is chosen for the printed circuit board (PCB) board-level S-parameter extraction, while Tektronix oscilloscope (TDS7404) is used for the DDR3 waveform measurement. The lab measurement shows good agreement between simulation and measurement. The study shows that the combination of PowerSI and Hspice is recommended for quick system-level DDR3 SI simulation.展开更多
As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrati...As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.展开更多
Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integ...Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit (IC)is designed and realized in CSMC ' s 0. 6 μm CMOS ( complementary metal-oxide-semiconductor transistor ) technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation (FES) circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows: the output resistor is 118 ml), the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat' s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat' s sciatic nerve bundle and on the spinal cord.展开更多
The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m s...The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m series to do non-coherent integration. It is indicated that the power in- creasing times of larger target sidelobe is less than the power increasing times of smaller target main- lobe because of the larger target' s pseudo-randomness. Smaller target is integrated from larger tar- get sidelobe, which strengthens the detection capability of radar for smaller targets. According to the sidelobes distributing characteristic, a method is presented in this paper to remove the estimated sidelobes mean value for signal detection after non-coherent integration. Simulation results present that the SNR of small target can be improved approximately 6. 5 dB by the proposed method.展开更多
The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received dig...The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient ($11) and signal transmission coefficient ($21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft.展开更多
A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap refere...A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage's frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.展开更多
The application of Global Navigation Satellite Systems(GNSSs)in the intelligent railway systems is rapidly developing all over the world.With the GNSs-based train positioning and moving state perception,the autonomy a...The application of Global Navigation Satellite Systems(GNSSs)in the intelligent railway systems is rapidly developing all over the world.With the GNSs-based train positioning and moving state perception,the autonomy and flexibility of a novel train control system can be greatly enhanced over the existing solutions relying on the track-side facilities.Considering the safety critical features of the railway signaling applications,the GNSS stand-alone mode may not be sufficient to satisfy the practical requirements.In this paper,the key technologies for applying GNSS in novel train-centric railway signaling systems are investigated,including the multi-sensor data fusion,Virtual Balise(VB)capturing and messaging,train integrity monitoring and system performance evaluation.According to the practical characteristics of the novel train control system under the moving block mode,the details of the key technologies are introduced.Field demonstration results of a novel train control system using the presented technologies under the practical railway operation conditions are presented to illustrate the achievable performance feature of autonomous train state perception using BeiDou Navigation Satellite System(BDS)and related solutions.It reveals the great potentials of these key technologies in the next generation train control system and other GNSS-based railway implementations.展开更多
Ubiquitous radar is a new radar system that provides continuous and uninterrupted multifunction capability within a coverage volume. Continuous coverage from close-in "pop-up" targets in clutter to long-range target...Ubiquitous radar is a new radar system that provides continuous and uninterrupted multifunction capability within a coverage volume. Continuous coverage from close-in "pop-up" targets in clutter to long-range targets impacts selection of waveform parameters. The coherent processing interval (CPI) must be long enough to achieve a certain signal-to-noise ratio (SNR) that ensures the efficiency of detection. The condition of detection in the case of low SNR is analyzed, and three different cases that would occur during integration are discussed and a method to determine the CPI is presented. The simulation results show that targets detection with SNR as low as -26 dB in the experimental system can possibly determine the CPI.展开更多
The system model of embedded reconfigurable system is discussed firstly, followed by the construction of the soft- ware and hardware platform. Based on the platform, the function trait and control models of digital si...The system model of embedded reconfigurable system is discussed firstly, followed by the construction of the soft- ware and hardware platform. Based on the platform, the function trait and control models of digital signal processing tasks are described. According the functional unit model and control model, a software/hardware integrating model with dataflow control infrastructure is constructed. The software/hardware partition is carded out in the experiments of ultrasonic signal processing, and the results show that the system model is practicable.展开更多
随着军用无人机等航电系统不断朝着小型化、智能化、综合化的方向发展,如何有效满足装备的低SWaP(Size,Weight and Power)要求成为一大难题。介绍了某型宽带综合化数字预处理模块的研制,利用“裸芯片+高密度基板”系统级封装(SiP)的方...随着军用无人机等航电系统不断朝着小型化、智能化、综合化的方向发展,如何有效满足装备的低SWaP(Size,Weight and Power)要求成为一大难题。介绍了某型宽带综合化数字预处理模块的研制,利用“裸芯片+高密度基板”系统级封装(SiP)的方式对信号处理平台(DSP、FPGA、SerDes和DDR芯片)进行集成,替代目前业界普遍采用的“封装芯片+印制板+平面集成”的传统方式,实现宽带综合化数字信号处理模块的高密度集成。在主要性能指标(可编程逻辑资源、定点处理能力、浮点处理能力、数据传输速率)不变的情况下,使得信号处理模块的面积降低为45 mm×45 mm,重量降低到103 g。展开更多
A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the S...A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the Si substrate. The substrate pn junction can be realized by using the standard silicon technologies without any additional processing steps.Integrated inductors on silicon are designed and fabricated. S parameters of the inductor based equivalent circuit are investigated and the inductor parameters are calculated.The impacts of the substrate pn junction isolation on the inductor quality factor are studied.The experimental results show that substrate pn junction isolation in certain depth has achieved a significant improvement.At 3GHz,the substrate pn junction isolation increases the inductor quality factor by 40%.展开更多
In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor...In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor(CMOS) on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.展开更多
基金Supported by Macao Science and Technology Development Fund,No.0086/2022/A and No.0097/2022/A2.
文摘In this article,we comment on the article by Huang et al.The urgent development of new therapeutic strategies targeting macrophage polarization is critical in the fight against liver cancer.Tumor-associated macrophages(TAMs),primarily of the M2 subtype,are instrumental in cellular communication within the tumor microenvironment and are influenced by various signaling pathways,including the wingless/integrated(Wnt)pathway.Activation of the Wnt signaling pathway is pivotal in promoting M2 TAMs polarization,which in turn can exacerbate hepatocarcinoma cell proliferation and migration.This manuscript emphasizes the burgeoning significance of the Wnt signaling pathway and M2 TAMs polarization in the pathogenesis and progression of liver cancer,highlighting the potential therapeutic benefits of inhibiting the Wnt pathway.Lastly,we point out areas in Huang et al’s study that require further research,providing guidance and new directions for similar studies.
文摘The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
文摘The device is used for the test on the fuze detonating time according to the initial velocity of the projectile and the altitude and speed of enemy aircraft flight. For the special requirements of the high-speed signal acquisition in the process, the characteristics of the measured signal are analyzed. The system is investigated in chip selection, signal transmission, signal processing, signal storage, post-production PCB design, etc. The appropriate measures and solutions which affect the integrity and accuracy of the signal in each process are proposed. The rules for the layout of the device and wiring are made. The result show that the measurement values are accurate without loss of data.
基金Supported by the National Natural Science Foundation of China(NSFC 62105100)the National Key research and development program in the 14th five year plan(2021YFA1200700)。
文摘Silicon(Si)diffraction microlens arrays are usually used to integrating with infrared focal plane arrays(IRFPAs)to improve their performance.The errors of lithography are unavoidable in the process of the Si diffrac-tion microlens arrays preparation in the conventional engraving method.It has a serious impact on its performance and subsequent applications.In response to the problem of errors of Si diffraction microlens arrays in the conven-tional method,a novel self-alignment method for high precision Si diffraction microlens arrays preparation is pro-posed.The accuracy of the Si diffractive microlens arrays preparation is determined by the accuracy of the first li-thography mask in the novel self-alignment method.In the subsequent etching,the etched area will be protected by the mask layer and the sacrifice layer or the protective layer.The unprotection area is carved to effectively block the non-etching areas,accurately etch the etching area required,and solve the problem of errors.The high precision Si diffraction microlens arrays are obtained by the novel self-alignment method and the diffraction effi-ciency could reach 92.6%.After integrating with IRFPAs,the average blackbody responsity increased by 8.3%,and the average blackbody detectivity increased by 10.3%.It indicates that the Si diffraction microlens arrays can improve the filling factor and reduce crosstalk of IRFPAs through convergence,thereby improving the perfor-mance of the IRFPAs.The results are of great reference significance for improving their performance through opti-mizing the preparation level of micro nano devices.
基金DST-SERB(Government of India)for research funding(No.CRG/2021/000513,dated 15/12/2021)UGC-CAS and DST-FIST(Government of India)for infrastructural support for research to the Department of Botany,University of Burdwan,India[No.F.5-13/012(SAP-II),and No.SRFST/LSI/2018/188(C)]+4 种基金the University Grants Commission(UGC),New Delhi,for Junior Research Fellowship(Joint CSIR-UGC)the State Funded Research Grant,Government of West Bengal.India[No.FC(Sc.)/RS/SF/BOT/2016-17/210/1(4)]Department of Science Technology and Biotechnology(DSTBT),Government of West Bengal.IndiaIndian Council for Cultural Relations(ICCR)for India Scholarships(Bangladesh)Scheme,2016-2017(No.DAC/EDU/17/1/2016,dated 10.07.2016)DST-SERB,Government of India.
文摘The elaborate redox network of the cell,comprising of events like turnover of reactive oxygen species(ROS),redox sensing,signaling,expression of redox-sensitive genes,etc.,often orchestrates with other bonafide hormonal signaling pathways through their synergistic or antagonistic action in the plant cell.The redox cue generated in plant cells under fluctuating environmental conditions can significantly influence other hormonal biosynthetic or signaling mechanisms,thereby modulating physiology towards stress acclimation and defense.There is also strong evidence of the recruitment of ROS as a‘second messenger’in different hormonal signaling pathways under stress.Moreover,the retrograde signaling initiated by ROS also found to strongly influence hormonal homeostasis and signaling.The present review,in this aspect,is an effort towards understanding the regulatory roles of ROS in integrating and orchestrating other hormonal signaling pathways or vice versa so as to unfold the relationship between these two signaling episodes of plant cells under environmental odds.We also accentuate the significance of understanding the utterly complex interactions,which occur both at metabolic and genetic levels between ROS and phytohormones during stress combinations.Furthermore,the significant and decisive role of ROS turnover,particularly the contribution of RBOH(respiratory burst oxidase homologs)in the synergism of redox and hormone signaling during systemic acquired acclimation under stress is also discussed.
基金supported by the National Natural Science Foundation of China under Grant No.61161001
文摘---Double data rate synchronous dynamic random access memory (DDR3) has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integrity (SI) simulation flow for the DDR3 interface, two system-level SI simulation methodologies, which are board-level S-parameter extraction in the frequency-domain and system-level simulation assumptions in the time domain, are introduced in this paper. By comparing the flow of Speed2000 and PowerSI/Hspice, PowerSI is chosen for the printed circuit board (PCB) board-level S-parameter extraction, while Tektronix oscilloscope (TDS7404) is used for the DDR3 waveform measurement. The lab measurement shows good agreement between simulation and measurement. The study shows that the combination of PowerSI and Hspice is recommended for quick system-level DDR3 SI simulation.
文摘As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.
基金The National Natural Science Foundation of China(No.90307013,90707005)
文摘Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit (IC)is designed and realized in CSMC ' s 0. 6 μm CMOS ( complementary metal-oxide-semiconductor transistor ) technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation (FES) circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows: the output resistor is 118 ml), the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat' s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat' s sciatic nerve bundle and on the spinal cord.
基金Supported by the National Natural Science Foundation of China(Youth Science Fund)(61001190)
文摘The m series with 511 bits is taken as an example being applied in non-coherent integra- tion algorithm. A method to choose the bi-phase code is presented, which is 15 kinds of codes are picked out of 511 kinds of m series to do non-coherent integration. It is indicated that the power in- creasing times of larger target sidelobe is less than the power increasing times of smaller target main- lobe because of the larger target' s pseudo-randomness. Smaller target is integrated from larger tar- get sidelobe, which strengthens the detection capability of radar for smaller targets. According to the sidelobes distributing characteristic, a method is presented in this paper to remove the estimated sidelobes mean value for signal detection after non-coherent integration. Simulation results present that the SNR of small target can be improved approximately 6. 5 dB by the proposed method.
基金Project supported by the National Natural Science Foundation of China(Grant No.61204044)
文摘The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient ($11) and signal transmission coefficient ($21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft.
文摘A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage's frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.
基金supported by National Key Research and Development Program of China(2022YFB4300501)National Natural Science Foundation of China(62027809,U2268206,T2222015).
文摘The application of Global Navigation Satellite Systems(GNSSs)in the intelligent railway systems is rapidly developing all over the world.With the GNSs-based train positioning and moving state perception,the autonomy and flexibility of a novel train control system can be greatly enhanced over the existing solutions relying on the track-side facilities.Considering the safety critical features of the railway signaling applications,the GNSS stand-alone mode may not be sufficient to satisfy the practical requirements.In this paper,the key technologies for applying GNSS in novel train-centric railway signaling systems are investigated,including the multi-sensor data fusion,Virtual Balise(VB)capturing and messaging,train integrity monitoring and system performance evaluation.According to the practical characteristics of the novel train control system under the moving block mode,the details of the key technologies are introduced.Field demonstration results of a novel train control system using the presented technologies under the practical railway operation conditions are presented to illustrate the achievable performance feature of autonomous train state perception using BeiDou Navigation Satellite System(BDS)and related solutions.It reveals the great potentials of these key technologies in the next generation train control system and other GNSS-based railway implementations.
文摘Ubiquitous radar is a new radar system that provides continuous and uninterrupted multifunction capability within a coverage volume. Continuous coverage from close-in "pop-up" targets in clutter to long-range targets impacts selection of waveform parameters. The coherent processing interval (CPI) must be long enough to achieve a certain signal-to-noise ratio (SNR) that ensures the efficiency of detection. The condition of detection in the case of low SNR is analyzed, and three different cases that would occur during integration are discussed and a method to determine the CPI is presented. The simulation results show that targets detection with SNR as low as -26 dB in the experimental system can possibly determine the CPI.
基金supported by the Research Project of “SUST Spring Bud”under contract number 2008BW2046 fron Shandong University of Science and Technology,China
文摘The system model of embedded reconfigurable system is discussed firstly, followed by the construction of the soft- ware and hardware platform. Based on the platform, the function trait and control models of digital signal processing tasks are described. According the functional unit model and control model, a software/hardware integrating model with dataflow control infrastructure is constructed. The software/hardware partition is carded out in the experiments of ultrasonic signal processing, and the results show that the system model is practicable.
文摘A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the Si substrate. The substrate pn junction can be realized by using the standard silicon technologies without any additional processing steps.Integrated inductors on silicon are designed and fabricated. S parameters of the inductor based equivalent circuit are investigated and the inductor parameters are calculated.The impacts of the substrate pn junction isolation on the inductor quality factor are studied.The experimental results show that substrate pn junction isolation in certain depth has achieved a significant improvement.At 3GHz,the substrate pn junction isolation increases the inductor quality factor by 40%.
文摘In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor(CMOS) on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.