Capacitor self-calibration technique used in time-interleaved successive approximation ADC

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

The Successive Approximation Broyden-like Algorithm for Nonlinear Complementarity Problems

In this paper, we present a new form of successive approximation Broyden-like algorithm for nonlinear complementarity problem based on its equivalent nonsmooth equations. Under suitable conditions, we get the global convergence on the algorithms. Some numerical results are also reported.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

Non-Convex Optimization of Resource Allocation in Fog Computing Using Successive Approximation

Fog computing can deliver low delay and advanced IT services to end users with substantially reduced energy consumption.Nevertheless,with soaring demands for resource service and the limited capability of fog nodes,how to allocate and manage fog computing resources properly and stably has become the bottleneck.Therefore,the paper investigates the utility optimization-based resource allocation problem between fog nodes and end users in fog computing.The authors first introduce four types of utility functions due to the diverse tasks executed by end users and build the resource allocation model aiming at utility maximization.Then,for only the elastic tasks,the convex optimization method is applied to obtain the optimal results;for the elastic and inelastic tasks,with the assistance of Jensen’s inequality,the primal non-convex model is approximated to a sequence of equivalent convex optimization problems using successive approximation method.Moreover,a two-layer algorithm is proposed that globally converges to an optimal solution of the original problem.Finally,numerical simulation results demonstrate its superior performance and effectiveness.Comparing with other works,the authors emphasize the analysis for non-convex optimization problems and the diversity of tasks in fog computing resource allocation.

A New Successive Approximation Damped Newton Method for Nonlinear Complementarity Problems

In this paper, we present a new successive approximation damped Newton method for the nonlinear complementarity problem based on its equivalent nonsmooth equations. Under suitable conditions, we obtain the global convergence result of the proposed algorithms. Some numerical results are also reported.

An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers. A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity. Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm. An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype, fabricated in UMC 0.18 um CMOS technology, achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s. The total power consumption is 0.918 mW for a 1.8 V supply, while the onchip reference consumes 53% of the total power. It achieves a figure of merit of 180 fJ/conv-step, excluding the reference＇s power consumption.

A successive approximation method for quantum separability

Determining whether a quantum state is separable or inseparable （entangled） is a problem of fundamental importance in quantum science and has attracted much attention since its first recognition by Einstein, Podolsky and Rosen [Phys. Rev., 1935, 47： 777] and SchrSdinger [Naturwissenschaften, 1935, 23： 807-812, 823-828, 844-849]. In this paper, we propose a successive approximation method （SAM） for this problem, which approximates a given quantum state by a so-called separable state： if the given states is separable, this method finds its rank-one components and the associated weights; otherwise, this method finds the distance between the given state to the set of separable states, which gives information about the degree of entanglement in the system. The key task per iteration is to find a feasible descent direction, which is equivalent to finding the largest M-eigenvalue of a fourth-order tensor. We give a direct method for this problem when the dimension of the tensor is 2 and a heuristic cross-hill method for cases of high dimension. Some numerical results and experiences are presented.

A low power 8-bit successive approximation register A/D for a wireless body sensor node

A power efficient 8-bit successive approximation register（SAR） A/D for the vital sign monitoring of a wireless body sensor network（WBSN） is presented.A charge redistribution architecture is employed.The prototype A/D is fabricated in 0.18μm CMOS.The A/D achieves 7.5ENOB with sampling rate varying from 64 kHz to 1.5 MHz. The power consumption varies from 10.8 to 225.7μW.

A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.

A 72-dB-SNDR rail-to-rail successive approximation ADC using mismatch calibration techniques

When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introduces an improved successive approximation ADC, which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ/conversion-step.

APPROXIMATION OF SOLUTION OF LINEAR DIFFERENTIAL EQUATION WITH ALMOST PERIOD FUNCTION COEFFICIENTS

This paper is devoted to the study of approximation of the solution for the differential equation whose coefficients are almost period functions. To this end the authors establish the estimation of the solution of general linear differential equation for infinite interval case. For finite interval case, this equation was investigated by G. Tamarkin([1]) applying the Picard method of successive approximation.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

Numerical Study of the Vibrations of Beams with Variable Stiffness under Impulsive or Harmonic Loading

The behavior of beams with variable stiffness subjected to the action of variable loadings (impulse or harmonic) is analyzed in this paper using the successive approximation method. This successive approximation method is a technique for numerical integration of partial differential equations involving both the space and time, with well-known initial conditions on time and boundary conditions on the space. This technique, although having been applied to beams with constant stiffness, is new for the case of beams with variable stiffness, and it aims to use a quadratic parabola (in time) to approximate the solutions of the differential equations of dynamics. The spatial part is studied using the successive approximation method of the partial differential equations obtained, in order to transform them into a system of time-dependent ordinary differential equations. Thus, the integration algorithm using this technique is established and applied to examples of beams with variable stiffness, under variable loading, and with the different cases of supports chosen in the literature. We have thus calculated the cases of beams with constant or variable rigidity with articulated or embedded supports, subjected to the action of an instantaneous impulse and harmonic loads distributed over its entire length. In order to justify the robustness of the successive approximation method considered in this work, an example of an articulated beam with constant stiffness subjected to a distributed harmonic load was calculated analytically, and the results obtained compared to those found numerically for various steps (spatial h and temporal τ ¯ ) of calculus, and the difference between the values obtained by the two methods was small. For example for ( h=1/8 , τ ¯ =1/ 64 ), the difference between these values is 17%.

ASYMPTOTIC STABILITY OF RAREFACTION WAVE FOR GENERALIZED BURGERS EQUATION

This paper is concerned with the stability of the rarefaction wave for the Burgers equationwhere 0 ≤ a < 1/4p (q is determined by (2.2)). Roughly speaking, under the assumption that u_ < u+, the authors prove the existence of the global smooth solution to the Cauchy problem (I), also find the solution u(x, t) to the Cauchy problem (I) satisfying sup |u(x, t) -uR(x/t)| → 0 as t → ∞, where uR(x/t) is the rarefaction wave of the non-viscous Burgersequation ut + f(u)x = 0 with Riemann initial data u(x, 0) =

EXISTENCE OF GLOBAL SMOOTH SOLUTION FOR SCALAR CONSERVATION LAWS WITH DEGENERATE VISCOSITY IN 2-DIMENSIONAL SPACE

This article concerns the existence of global smooth solution for scalar conservation laws with degenerate viscosity in 2-dimensional space. The analysis is based on successive approximation and maximum principle.

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

This paper analyzes the power consumption and delay mechanisms of the successive-approximation （SA） logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203μW.

SOLITARY WAVES IN STRATIFIED FLUIDS AND THEIR INTERACTION

A systematic procedure is proposed for obtaining solutions for soli- tary waves in stratified fluids. The stratification of the fluid is assumed to be expo- nential or linear. Its comparison with existing results for an exponentially stratified fluid shows agreement, and it is found that for the odd series of solutions the direc- tion of displacement of the streamlines from their asymptotic levels is reversed when the stratification is changed from exponential to linear. Finally the interaction of solitary waves is considered, and the Korteweg-de Vries equation and the Boussinesq equation are derived. Thus the known solutions of these equations can be rehed upon to provide the answers to the interaction problem.

An SQP algorithm for mathematical programs with nonlinear complementarity constraints

In this paper, we describe a successive approximation and smooth sequential quadratic programming （SQP） method for mathematical programs with nonlinear complementarity constraints （MPCC）. We introduce a class of smooth programs to approximate the MPCC. Using an 11 penalty function, the line search assures global convergence, while the superlinear convergence rate is shown under the strictly complementary and second-order sufficient conditions. Moreover, we prove that the current iterated point is an exact stationary point of the mathematical programs with equilibrium constraints （MPEC） when the algorithm terminates finitely.