5 Msample/s两倍增益差分采样/保持电路的设计和分析

设计和分析了一种用于10位分辨率,5MHz采样频率流水线式模数转换器中的差分采样/保持电路。该电路是采用电容下极板采样、开关栅电压自举、折叠式共源共栅技术进行设计,有效地消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差,提高了采样电路的线性度,节省了芯片面积、功耗。电路是在0.6μm CMOS工艺下进行模拟仿真,当输入正弦波频率为500kHz,采样频率为5MHz时,电路地无杂散动态范围(SFDR)为75.4dB,能够很好的提高电路的信噪比,因此该电路适用于流水线式模数转换器。

一种14位105 Msample/s高速高精度模数转换器设计

采用4位量化增益数模单元实现了流水线的第一级子级和最后一级采用4位FLASH ADC组成的系统架构,设计了一款基于流水线型的14位105 MHz采样速率的高速高精度模数转换器。多位量化较好地抑制了后级电路的噪声和失真衰减,采用采样电容翻转式结构实现了采样保持电路,在较高采样速率下,尽量降低功耗。电路采用SMIC 0.18μm混合信号工艺进行设计验证,测试结果表明,在输入信号频率为70 MHz,采样速率为105 MHz时,无杂散动态范围为84.2 dB,信噪比为73.2 dB,有效位数约为11.8 bit。

Fault Current Identification of DC Traction Feeder Based on Optimized VMD and Sample Entropy

A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.

A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters

A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.

A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.

Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Computer Program Calculation for Distortion of Wide-Band Track and Hold Amplifier

Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.

Finite rate of innovation sparse sampling for a binary frequency-coded ultrasonic signal

To achieve sparse sampling on a coded ultrasonic signal,the finite rate of innovation(FRI)sparse sampling technique is proposed on a binary frequency-coded(BFC)ultrasonic signal.A framework of FRI-based sparse sampling for an ultrasonic signal pulse is presented.Differences between the pulse and the coded ultrasonic signal are analyzed,and a response mathematical model of the coded ultrasonic signal is established.A time-domain transform algorithm,called the high-order moment method,is applied to obtain a pulse stream signal to assist BFC ultrasonic signal sparse sampling.A sampling of the output signal with a uniform interval is then performed after modulating the pulse stream signal by a sampling kernel.FRI-based sparse sampling is performed using a self-made circuit on an aluminum alloy sample.Experimental results show that the sampling rate reduces to 0.5 MHz,which is at least 12.8 MHz in the Nyquist sampling mode.The echo peak amplitude and the time of flight are estimated from the sparse sampling data with maximum errors of 9.324%and 0.031%,respectively.This research can provide a theoretical basis and practical application reference for reducing the sampling rate and data volume in coded ultrasonic testing.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

基于SiGe BiCMOS工艺的8 GS/s采样保持电路

为实现数字通信对高速模数转换器的要求,基于0.18μm SiGe BiCMOS工艺提出了一款8 GS/s采样率、6 bit的采样保持电路。电路采用全差分开环结构,利用射极跟随型采样开关实现了电路高采样率。采样开关中采用晶体管线性补偿技术,有效地提高了采样保持电路的线性度。输出缓冲电路采用级联结构实现高线性度,并提高了电路的驱动能力。测试结果发现,在采样模式下单端输入信号频率4 GHz、采样时钟频率8 GHz条件下,有效位数为5.4 bit,无杂散动态范围为37.6 dB,总谐波失真为37.5 dB,总功耗为450 mW,芯片尺寸为0.68 mm×0.68 mm。

适用小样本的并网光伏阵列故障诊断方法

该文提出一种适用小样本的并网光伏阵列故障诊断方法。首先,使用光伏阵列的稳态输出电信号时间序列构建特征向量,论证该特征向量可以表征正常、开路故障、短路故障、阴影等不同状态。其次,针对光伏阵列运行环境多变的情况,提出一种将实际气象条件下光伏阵列输出值转换到统一工况下的数据处理方法。然后,为适用小样本情况,将线性判别分析方法与有偏差的协方差估计、公共奇异值分解相结合,解决样本高维低量导致的样本协方差矩阵估计奇异和判别函数求解困难的问题。最后,在上海市某高校楼顶搭建实验平台,采集光伏阵列不同状态下的实验数据,验证了所提数据处理方法对使用稳态电信号的必要性,及该故障分类算法在小样本场景中的有效性。

基于临界超标样本扩充的数据驱动短路电流超标精准校验方法

短路电流超标校验中,针对现有技术在临界超标场景下存在计算精度不足、易误判的缺陷,提出一种基于临界超标样本扩充的数据驱动短路电流超标精准校验方法。首先,在短路电流领域首次采用生成对抗网络(generative adversarial networks,GAN)产生与蒙特卡洛模拟具有相同效力的大量样本,再筛选其中的临界超标样本;其次,设计了一种临界超标占比高、非临界超标占比低的新型样本构成方式,据此融合GAN生成临界超标样本与蒙特卡洛仿真样本以形成数据驱动样本集;继而,采用数据驱动的代表性回归算法LightGBM开展短路电流超标校验;最后,仿真结果表明所提方法能有效提高短路电流超标的校验准确度,相比其他物理计算方法和数据驱动方法具有更高效率和计算精度,以及更快的计算速度。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

高光谱应用的带可调复位时间CDS的低噪声红外焦平面读出电路

低辐射量的高光谱应用对红外焦平面读出电路(ROIC)提出了低噪声的设计要求。相关双采样(CDS)是常用的减少噪声的结构。本文通过调节钳位和采样保持之间的时间间隔来改进CDS,可灵活消除低频噪声。采用180 nm CMOS工艺设计和制造了640×512规模、15μm像元中心距的读出电路。输入级集成了低噪声CTIA与本文提出的可调复位时间CDS(AICDS),所设计的时序产生器使CDS复位时间可以延长0~270个时钟周期。通过延长复位时间减少这个时间间隔,噪声电子数可以由39 e^(-)减少到18.3 e^(-)。SPECTRE仿真结果和实验测试结果证实了提出的AICDS结构可以提升高光谱应用读出电路的噪声性能,因此可以广泛应用。

MEMS陀螺仪高精度低噪声检测电路设计

为满足电容式MEMS陀螺仪低噪声,高精度的检测需求,设计了一款基于开关电容结构的全差分检测电路,主要包括电容检测和数字量化处理两部分。电容检测电路采用离散时间电容电压(C/V)转换方案,提出将高频载波调制和相关双采样技术相结合的方式,有效降低了低频噪声的干扰。量化电路采用一款4阶4 bit单环前馈结构的带通ΔΣ调制器,输入信号前馈通路的引入提高了系统的稳定性,内部多位量化器有效提高了信噪比。系统在保持低功耗的同时实现了高精度输出。基于0.18μm BCD工艺,在5 V电源电压下,对整体电路进行仿真验证。仿真结果表明,检测电路灵敏度可以实现10 m V/f F,在谐振频率5 k Hz处,等效输入电容噪声为■。最终在100 Hz带宽范围内,读出信号量化精度可以达到15 bits。与传统的MEMS陀螺仪检测电路相比,该电路具有更低的噪声和更高的量化精度,能够满足高精度检测应用需求。

阿波罗月球样品介电参数测试综述

介电常数是衡量月球介电特性的重要参数。利用月球介电参数可以反演月壤厚度、密度等重要物性参数,有助于研究月球地质构造和地质演化历史。获取月表介电参数的方法主要为雷达远程遥测、月表雷达就位探测和月球样品测量,其中月球样品测量是最为直接有效的测量方式。阿波罗任务总共获得了约381 kg月球样品,总结了阿波罗月球样品介电参数测量方法,分析了测试结果。测试结果表明,频率、温度、湿度、密度和氧化物等因素会影响样品介电参数测量。在后续样品介电测试中,需要考虑这些因素。

基于PLC的核电站一回路水化学监测自动取样系统设计

为了及时、便捷、无污染地获取核电站一回路水质样品,提高水质监测效率,设计了基于PLC的核电站一回路水化学监测自动取样系统。首先对自动取样系统工艺组成进行分析,提出功能需求,设计由现场层、过程层和管理层构成的总体方案,然后介绍各层级硬件组成以及层级间的连接关系,最后,设计过程层PLC的软件程序实现自动取样系统热工参数的实时测量、自动控制和超限保护,设计管理层工业控制计算机人机界面实现参数可视化、存储和报警提示。采用经典的PID算法实现热工参数自动控制,通过理论建模与经验试凑相结合的方式提升PID参数调试效率,并进行手自动无扰切换处理提升自动控制算法的稳定性。经验证,该系统可以稳定、自动获取样品,对提高核电站一回路水化学监测自动化水平有重要意义。

基于锂电池均衡保护芯片的电压采样电路设计

针对锂电池均衡保护问题,设计一种基于锂电池均衡保护芯片的电压采样电路。采用主动均衡的方式对锂电池进行均衡保护。电压采样电路采样两节锂电池电压以监测锂电池的差异性,并通过8位逐次逼近型数模转换器进行数据转换。运用均衡控制逻辑分析转换的数据,对锂电池执行均衡保护。采用华虹NEC 0.18μm BCD工艺进行设计并通过仿真验证。仿真结果表明,电压采样电路有较高的电压采样精度,逐次逼近型数模转换器的有效位数等指标均有优秀的性能表现。本研究能够可靠地采样各电池的电压,适用于锂电池均衡保护芯片的应用场合,有利于延长电池组的使用时间。

基于0.18μm CMOS工艺的低功耗采样保持电路

基于0.18μm CMOS工艺设计了一款用于ADC前端的采样保持电路,电路采用输入缓冲器-采样开关-输出缓冲器三级结构实现。为提高采样保持电路的保持平稳度,设计了信号馈通和时钟馈通消除结构。为改善频率响应,设计了无源负反馈结构并研究了器件参数对电路性能的影响。仿真结果表明,该馈通消除结构能够提升保持阶段的平稳度,负反馈可将增益提升36 dB。该电路在800 MS/s采样率、122.6 MHz正弦波输入条件下,增益为0 dB,3 dB带宽为1 GHz,信号失真比为48 dB,有效位数为7.7 bit。最终版图面积为202μm×195μm,功耗为37.22 mW,实现了低功耗的设计目标。

醇基燃料热值检测试验中盛样装置的研究

为防止醇基燃料在热值检测试验中的样品挥发,从而引起检测结果精密度差,通过采用恒温室全自动量热仪对醇基燃料的热值进行测定,分别采用药用胶囊、聚乙烯安剖瓶和生料带封口燃烧皿对样品进行密封测量,通过大量实验,计算三种试验数据的相对标准偏差,分析三种盛样方法的优缺点,从而研究出醇基燃料在取样和检测过程中能有效防止样品挥发且容易获得的一种盛样装置,为醇基燃料热值的准确检测提供基础保障,助推醇基燃料的广泛使用。