20 MHz Switched-Current Sample-and-Hold Circuit with Low Charge Injection

A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and -51.24 dB to 56.53 dB and -54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.

Fault Current Identification of DC Traction Feeder Based on Optimized VMD and Sample Entropy

A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.

5 Msample/s两倍增益差分采样/保持电路的设计和分析

设计和分析了一种用于10位分辨率,5MHz采样频率流水线式模数转换器中的差分采样/保持电路。该电路是采用电容下极板采样、开关栅电压自举、折叠式共源共栅技术进行设计,有效地消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差,提高了采样电路的线性度,节省了芯片面积、功耗。电路是在0.6μm CMOS工艺下进行模拟仿真,当输入正弦波频率为500kHz,采样频率为5MHz时,电路地无杂散动态范围(SFDR)为75.4dB,能够很好的提高电路的信噪比,因此该电路适用于流水线式模数转换器。

一种14位105 Msample/s高速高精度模数转换器设计

采用4位量化增益数模单元实现了流水线的第一级子级和最后一级采用4位FLASH ADC组成的系统架构,设计了一款基于流水线型的14位105 MHz采样速率的高速高精度模数转换器。多位量化较好地抑制了后级电路的噪声和失真衰减,采用采样电容翻转式结构实现了采样保持电路,在较高采样速率下,尽量降低功耗。电路采用SMIC 0.18μm混合信号工艺进行设计验证,测试结果表明,在输入信号频率为70 MHz,采样速率为105 MHz时,无杂散动态范围为84.2 dB,信噪比为73.2 dB,有效位数约为11.8 bit。

Minimizing crosstalk for high-speed and high-density bus systems using the sample-decision method

This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.

基于SiGe BiCMOS工艺的8 GS/s采样保持电路

为实现数字通信对高速模数转换器的要求,基于0.18μm SiGe BiCMOS工艺提出了一款8 GS/s采样率、6 bit的采样保持电路。电路采用全差分开环结构,利用射极跟随型采样开关实现了电路高采样率。采样开关中采用晶体管线性补偿技术,有效地提高了采样保持电路的线性度。输出缓冲电路采用级联结构实现高线性度,并提高了电路的驱动能力。测试结果发现,在采样模式下单端输入信号频率4 GHz、采样时钟频率8 GHz条件下,有效位数为5.4 bit,无杂散动态范围为37.6 dB,总谐波失真为37.5 dB,总功耗为450 mW,芯片尺寸为0.68 mm×0.68 mm。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

高光谱应用的带可调复位时间CDS的低噪声红外焦平面读出电路

低辐射量的高光谱应用对红外焦平面读出电路(ROIC)提出了低噪声的设计要求。相关双采样(CDS)是常用的减少噪声的结构。本文通过调节钳位和采样保持之间的时间间隔来改进CDS,可灵活消除低频噪声。采用180 nm CMOS工艺设计和制造了640×512规模、15μm像元中心距的读出电路。输入级集成了低噪声CTIA与本文提出的可调复位时间CDS(AICDS),所设计的时序产生器使CDS复位时间可以延长0~270个时钟周期。通过延长复位时间减少这个时间间隔,噪声电子数可以由39 e^(-)减少到18.3 e^(-)。SPECTRE仿真结果和实验测试结果证实了提出的AICDS结构可以提升高光谱应用读出电路的噪声性能,因此可以广泛应用。

适用小样本的并网光伏阵列故障诊断方法

该文提出一种适用小样本的并网光伏阵列故障诊断方法。首先,使用光伏阵列的稳态输出电信号时间序列构建特征向量,论证该特征向量可以表征正常、开路故障、短路故障、阴影等不同状态。其次,针对光伏阵列运行环境多变的情况,提出一种将实际气象条件下光伏阵列输出值转换到统一工况下的数据处理方法。然后,为适用小样本情况,将线性判别分析方法与有偏差的协方差估计、公共奇异值分解相结合,解决样本高维低量导致的样本协方差矩阵估计奇异和判别函数求解困难的问题。最后,在上海市某高校楼顶搭建实验平台,采集光伏阵列不同状态下的实验数据,验证了所提数据处理方法对使用稳态电信号的必要性,及该故障分类算法在小样本场景中的有效性。

A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.

醇基燃料热值检测试验中盛样装置的研究

为防止醇基燃料在热值检测试验中的样品挥发,从而引起检测结果精密度差,通过采用恒温室全自动量热仪对醇基燃料的热值进行测定,分别采用药用胶囊、聚乙烯安剖瓶和生料带封口燃烧皿对样品进行密封测量,通过大量实验,计算三种试验数据的相对标准偏差,分析三种盛样方法的优缺点,从而研究出醇基燃料在取样和检测过程中能有效防止样品挥发且容易获得的一种盛样装置,为醇基燃料热值的准确检测提供基础保障,助推醇基燃料的广泛使用。

一种11bit流水线高速模数转换器

为解决流水线模数转换器(ADC)在连续工作时功耗高、电容器匹配度有限以及运算放大器大摆幅输出信号下线性度下降的问题,基于0.5μm BCD工艺,设计了一款11 bit流水线高速ADC。提出了无采样保持放大器、幅度减半和多位量化相结合的设计方法,使ADC在大摆幅信号下有足够的线性度来处理信号,同时使电容数模转换器(DAC)的匹配精度满足ADC分辨率的要求,极大地降低了对电容阵列几何参数的匹配精度要求,具有较低的功耗。采用Cadence Virtuoso设计版图,测试结果表明,芯片的微分非线性(DNL)在-0.5~+0.5 LSB范围内,有效位数(ENOB)为10.61 bit,功耗为97 mW,获得了较好的性能。

基于电磁铁回路电流值标准差的站台门自保持电磁锁系统故障诊断及预测方法

[目的]站台门电磁锁是城市轨道交通车站站台门的关键部件之一。电磁锁发生故障将直接影响线路的行车安全及乘客在站台的正常通行。在设备智能运维的发展趋势下,需要对站台门电磁锁的故障诊断及预测方法进行深入研究。[方法]简述了站台门自保持电磁锁系统工作原理,对自保持电磁锁3个故障种类下的8个子故障对正常运营的影响程度进行了分析。研究了电磁铁动作时的电流特性及故障时的电流特性,进一步对铁心卡滞、铁心未落到位、铁心吸合不到位3种故障工况进行研究。通过对不同故障工况下采集的电磁铁电流与正常状态下采集的电磁铁电流进行对比,进而得到该故障工况下电磁铁电流的特性。将故障工况下的电磁铁电路曲线与正常电磁铁标准曲线的标准差进行对比,从而实现对自保持电磁锁系统的故障诊断及预测。[结果及结论]故障工况下电磁铁电路曲线与正常电磁铁标准曲线的标准差越大,电磁铁发生故障的可能就越大。当采集得到的电磁铁电流与正常状态下电磁铁电流的标准差大于预警值时,可对该套门锁发出故障预警。

矿用成像设备的电路噪声抑制研究

高性能红外成像设备是实现煤矿井下设备状态实时在线监测与动态精准预测的有效手段,过大的噪声干扰可能淹没探测器信号,降低动态范围。通过研究相关双采样结构,分析了焦平面电路的噪声特点及噪声抑制机理,设计了64×1线列电路。实验表明,相关双采样结构可以有效抑制KTC噪声,降低电路输出总噪声。

电阻抗成像系统中采样信号电路的设计与实验验证

深入探讨了电阻抗成像(EIT)中的一个关键技术——采样信号电子电路的实现。详细阐述了电路的基本原理和技术要求,采用先进的电路设计理念和技术,基于高性能的FPGA双驱动系统设计一套肺通气可视化电阻抗成像设备的硬件电路,主要包括采样控制单元、压控恒流源模块、分时复用模块、差分放大电路和安全耐压隔离模块单元。讨论了采用控制单元和分时复用模块实现信号采集的方法。通过实验测试,验证了所设计的EIT硬件电路在信号采集过程中具有高精度和高稳定性的优点,能够满足临床肺通气成像的需求。

Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Computer Program Calculation for Distortion of Wide-Band Track and Hold Amplifier

Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

8位高速低功耗流水线型ADC优化设计研究

采用每级为1.5位精度的7级流水线结构,即7级子ADC设计一个8位80 MS/s的低功耗模数转换电路。通过设计精简且高效的数字校准和输出寄存模块,消除ADC实现过程中各种因素的影响,提高ADC的精度和信噪比。采用0.18μm CMOS工艺完成加工后,测得该ADC在输入信号为36.25 MHz,采样速率为80 MHz下的信噪比(SNR)为49.6 dB,有效位数(ENOB)接近8位,典型的功耗电流只有18 mA,整个ADC的芯片面积为0.5 mm^(2)。

一种用于Pipeline ADC的高线性度栅压自举开关

在流水线模数转换器(Pipeline ADC)电路中,栅压自举开关中的非线性电容会对开关管的导通电阻产生直接的影响,导致采样非线性。设计了一种三路径的高线性度栅压自举开关,采用三个自举电容,分别构成两条主路径和一条辅助路径,使得输入信号在通过两条主路径传输到开关管栅端时加快栅端电压的建立,同时利用辅助路径驱动非线性电容,减少电路中非线性电容对采样电路线性度的影响,从而增强信号驱动能力,提高整体电路的精度。本文设计的栅压自举开关应用于14 bit 500 MHz流水线ADC的采样保持电路中。采用TSMC 28 nm CMOS工艺进行电路设计。仿真结果表明,在输入频率为249 MHz,采样频率为500 MHz的条件下,该栅压自举开关的信噪比(SNDR)达到92.85 dB,无杂散动态范围(SFDR)达到110.98 dB。