A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarg...A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 d BFS, an SFDR of 97.6 d Bc for a 10 MHz input signal, while preserving an SFDR 〉 80 d Bc up to 300 MHz input frequency. The ADC consumes 430 mW from a1.8 V supply and occupies a 17 mm^2 active area.展开更多
基金Project supported by the National Science and Technology Major Project(No.2009ZX01034-002-001-016)
文摘A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 d BFS, an SFDR of 97.6 d Bc for a 10 MHz input signal, while preserving an SFDR 〉 80 d Bc up to 300 MHz input frequency. The ADC consumes 430 mW from a1.8 V supply and occupies a 17 mm^2 active area.
