Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advan-tages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal – oxide – silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (AlN), which has a thermal conductivity that is about 200 times higher than that of SiO2 (320 W·m ? 1·K? 1 versus 1.4 W·m? 1·K? 1). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electri-cal characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AlN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the appli-cations of SOI to high temperature conditions.

Reduction of self-heating effect in SOI MOSFET by forming a new buried layer structure

An inherent self-heating effect of the silicon-on-insulator (SOI) devices limits their application at high current levels. In this paper a novel solution to reduce the self-heating effect is proposed, based on N+ and O+ co-implantation into silicon wafer to form a new buried layer structure. This new structure was simulated using Medici program, and the temperature distribution and output characteristics were compared with those of the conventional SOI counterparts. As expected, a reduction of self-heating effect in the novel SOI device was observed.

A new physics-based self-heating effect model for 4H-SiC MESFETs

A new self-heating effect model for 4H-SiC MESFETs is proposed based on a combination of an analytical and a computer aided design （CAD） oriented drain current model. The circuit oriented expressions of 4H-SiC low-field electron mobility and incomplete ionization rate, which are related to temperature, are presented in this model, which are used to estimate the self-heating effect of 4H-SiC MESFETs. The verification of the present model is made, and the good agreement between simulated results and measured data of DC I - V curves with the self-heating effect is obtained.

Investigation and active suppression of self-heating induced degradation in amorphous InGaZnO thin film transistors

Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysis has been applied to explore the physics origin of self-heating induced degradation, where Joule heat is shortly accumulated by drain current and dissipated in repeated time cycles as a function of gate bias. Enhanced positive threshold voltage shift is observed at reduced heat dissipation time, higher drain current, and increased gate width. A physical picture of Joule heating assisted charge trapping process has been proposed and then verified with pulsed negative gate bias stressing scheme, which could evidently counteract the self-heating effect through the electric-field assisted detrapping process. As a result, this pulsed gate bias scheme with negative quiescent voltage could be used as a possible way to actively suppress self-heating related device degradation.

Self-catalyzed Effect and Cracking Risk in Mass Concrete Containing Micro-slag

The main results obtained from the experimental and engineering investigation on the heat evolution and cracking risk of a furnace concrete block were presented. The heat evolution of experimental mortars containing micro-slag under different environmental temperatures was instrumented in order to investigate the self-catalyzed effect, which was discovered in engineering. More-over,the thermal stress of the furnace concrete due to heat temperature rise was calculated to evaluate the cracking risk of mass concrete containing micro-slag due to self-catalyzed effect. The experimental results illustrate that with the development of hydration and initial temperature of mixture, the hydra-tion can be also accelerated and temperature of concrete will be continued to rise, which was the self-catalyzed effect. And the thermal stress due to self-catalyzed effect could not result in the cracking of furnace concrete.

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

Impact of ambient temperature on the self-heating effects in FinFETs

We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.

Numerical analysis of the self-heating effect in SGOI with a double step buried oxide

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator（SGOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs）,this paper proposes a novel device called double step buried oxide（BOX） SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.

应变SiGe SOI p-MOSFET温度特性研究

SiGe SOI p-MOSFET在高频、高速、低功耗、抗辐射方面具有极大的优势。但二氧化硅埋层较低的热导率以及SiGe材料较低的热稳定性,使器件内部自加热效应的减弱或消除成为提高器件温度特性的关键因素。对应变SiGe SOI p-MOSFET温度特性机理进行研究,给出了三种缓解MOS-FET器件内部自加热效应的结构,并对其效果进行对比分析。结果表明:DSOI结构不适宜于低压全耗尽型SOI器件;Si3N4-DSOI结构对自加热的改善幅度较小;Si3N4埋层结构效果最好,尤其在低温领域改善更为明显。

A novel interconnect optimal buffer insertion model considering the self-heating effect

Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.

关于“Mpemba Effect”实验的研究

从做"Mpemba Effect"实验入手,对实验现象进行观察,并从物理学及混沌学等方面对其进行了详尽的研究分析,说明此现象即热水比冷水结冰快现象产生的原因及条件,并进一步阐述液体分子间的自组织系统、液体内部组成和液体外部空气的对流及液体的蒸发等对此实验结果的影响程度。

AlGaAs/GaAs HBT E-M 模型直流参数的修正

在ＳｉＢＪＴＥＭ模型基础上，对其直流参数进行了修正，使其适应于ＡｌＧａＡｓ／ＧａＡｓＨＢＴ的直流特性：电流增益不是常量和自热效应．计算机模拟值与实测值在中电流和较大电流时相当吻合，这一结果支持了ＨＢＴ电路模拟．

温度对绝缘层上应变SiGe沟道p-MOSFET电学特性的影响

本文利用二维数值模拟方法,模拟分析了不同工作温度时绝缘层上应变SiGe沟道p-MOSFET的输出特性和亚阈值特性。结果表明:随着器件工作温度的不断提高,漏源饱和电流单调减小;亚阈值电流略有增大;亚阈值摆幅的改变量ΔS与温度基本上成线性关系;阈值电压不断地向正方向偏移。通过考虑自热效应的影响,不同Ge组分器件的漏源饱和电流均有不同程度的降低,且随着Ge组分的增加,漏源饱和电流的降低幅度增大。

自热效应下P-GaNHEMT的阈值漂移机理

随着GaN功率应用朝着更高集成度与更高功率密度的方向发展,器件的自热效应及可靠性问题将变得更加严重。提出了一种开态漏极电流注入技术,模拟器件自热状态用以研究100 V P-GaN HEMT器件在自热效应下的可靠性问题。研究结果表明,应力中器件自热温度可达40~150℃,阈值电压在应力后发生0.2~0.8 V的显著正向漂移。进一步通过室温与高温下的器件恢复研究以及电热仿真分析,证明了栅下区域与栅漏接入区域的高温极值点增强了该区域的受主型电子陷阱俘获行为并改变了栅极处载流子输运,这是导致P-GaN HEMT在自热效应下阈值电压不稳定性的主要原因,并建立了相对应的物理机理模型。

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.

SOI-MOS器件的自热效应仿真及产热机理研究

随着微电子器件日益微型化和高速化,自热效应已逐渐成为限制其性能提升的重要因素,深入理解纳米尺度器件产热机理对电子器件的设计和优化具有重要意义.针对绝缘体上硅金属-氧化物半导体场效应晶体管(SOIMOS)进行了电热仿真,基于漂移扩散模型详细计算和分析了焦耳热、重组热和帕尔贴-汤姆逊热的生成及其影响.计算结果显示,焦耳热在器件内是主要的功耗来源,主要分布在栅极下方的导电沟道处,最大值出现在漏极端.与此相比,重组热的量级极小,主要分布在沟道区和源漏结区,其对温度场和器件性能的影响较弱.帕尔贴-汤姆逊热与焦耳热的产热量级相当,会影响器件温度分布.然而,由于其在栅极下方存在独特的冷热源交替分布,加热效应和制冷效应得到了抵消,同时引起的温度变化集中在源漏电极下方,导致其对器件性能基本不产生影响.此外,帕尔贴-汤姆逊热的影响与边界条件有关,在基底散热时,忽略帕尔贴-汤姆逊热会导致温度场预测发生较大偏差,这对于评估器件的寿命和可靠性非常关键.

Dispersion effect on the current voltage characteristic of AlGaN/GaN high electron mobility transistors

The current voltage （IV） characteristics are greatly influenced by the dispersion effects in A1GaN/CaN high electron mobility transistors. The direct current （DC） IV and pulsed IV measurements are performed to give a deep investigation into the dispersion effects, which are mainly related to the trap and self-heating mechanisms. The results show that traps play an important role in the kink effects, and high stress can introduce more traps and defects in the device. With the help of the pulsed IV measurements, the trapping effects and self-heating effects can be separated. The impact of time constants on the dispersion effects is also discussed. In order to achieve an accurate static DC IV measurement, the steady state of the bias points must be considered carefully to avoid the dispersion effects.

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

Electrical characteristics of SiGe-on-insulator nMOSFET and SiGe-silicon-on-aluminum nitride nMOSFET

This paper investigates the electrical characteristics and temperature distribution of strained Si/SiGe n-type metal oxide semiconductor field effect transistor （nMOSFET） fabricated on silicon-on-aluminum nitride （SOAN） substrate. This novel structure is named SGSOAN nMOSFET. A comparative study of self-heating effect of nMOSFET fabricated on SGOI and SGSOAN is presented. Numerical results show that this novel SGSOAN structure can greatly eliminate excessive self-heating in devices, which gives a more promising application for silicon on insulator to work at high temperatures.