An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.

Ultra-Robust and High-Performance Rotational Triboelectric Nanogenerator by Bearing Charge Pumping

As an emerging technology to convert environmental high-entropy energy into electrical energy,triboelectric nanogenerator(TENG)has great demands for further enhancing the service lifetime and output performance in practical applications.Here,an ultra-robust and high-performance rotational triboelectric nanogenerator(R-TENG)by bearing charge pumping is proposed.The R-TENG composes of a pumping TENG(P-TENG),an output TENG(O-TENG),a voltage-multiplying circuit(VMC),and a buffer capacitor.The P-TENG is designed with freestanding mode based on a rolling ball bearing,which can also act as the rotating mechanical energy harvester.The output low charge from the P-TENG is accumulated and pumped to the non-contact O-TENG,which can simultaneously realize ultralow mechanical wear and high output performance.The matched instantaneous power of R-TENG is increased by 32 times under 300 r/min.Furthermore,the transferring charge of R-TENG can remain 95%during 15 days(6.4×10^(6)cycles)continuous operation.This work presents a realizable method to further enhance the durability of TENG,which would facilitate the practical applications of high-performance TENG in harvesting distributed ambient micro mechanical energy.

Research and Design of an On-Chip High Efficiency Dual-Output Charge Pump

To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.

An Improved Charge-Averaging Charge Pump for a Fractional-N Frequency Synthesizer

An improved charge-averaging charge pump and the corresponding circuit implementation are presented. The charge-averaging charge pump proposed by Koo is analyzed and a new scheme is proposed. This new scheme decreases power by 1/3 and eliminates the practical defects in the original. Spectre Verilog behavioral simulation results show that the proposed scheme can strongly reduce the energy of spurs. Circuit implementation of this new charge pump for a frequency synthesizer with a fractional division ratio of 1/3 is then presented and multi-level simulation is performed to validate its feasibility at the circuit level. The simulation results show this new scheme outputs a flat voltage curve in a locked state and can thus effectively suppress fraction spurs.

基于Charge Pump技术的低压高频Antiringing MOS开关驱动电路

本文给出了一种基于Charge Pump适用于低压高频Antiringing MOS开关的驱动电路。该驱动电路工作电压最低可达1.8V,工作频率最高达5MHz。文章从Charge Pump及Antiringing的基本原理出发详细介绍了此驱动电路设计思想,并且给出最终设计电路。该电路基于Samsung 0.65-μm BiCMOS工艺设计,经过HSPICE仿真验证。

基于dikson charge pump的voltage doubler设计

随着集成电路工艺的发展,电源电压不断降低,使得charge pump在芯片上的地位更加重要。传统的voltage doubler基于开关的实现方法,由于MOS管阈值电压的影响,使得voltagedoubler的输出电压与2VDD电平相差甚远。在分析dikson charge pump工作原理的基础上,提出了一种新型的基于dikson charge pump的voltage doubler,通过外加电容的方法,可以实现对diksoncharge pump的输出电压进行微调,从而得到所需要的2VDD的电平。采用smic0.35μm工艺仿真后发现当VDD=5V时,传统的voltage doubler输出电平为8.54V,而dikson voltage doubler的输出电平为理想的10V。

A Novel All-pMOS AC to DC Charge Pump with High Efficiency

A novel AC to DC charge pump with high performance is presented. Due to the pMOS structure and threshold voltage canceling technology, the efficiency and the output voltage are greatly improved. Test results show that the output voltage and power efficiency are improved by 125% and 104% respectively at 13.56MHz for a 1V sinusoidal input compared to the traditional MOS diodes structure.

一种使Charge-pump的输出电压稳定的时钟电路

随着工艺的提高和电源电压的降低,需要能够在低电压下工作的电路。该文介绍了一种能在1.8V电压下工作的时钟产生器。它的频率随着电源电压的增大而减小,随着温度的升高而增大,并能抑制制程的偏差对频率产生的影响。从而使Charge-pump的输出电压稳定。

An Improved Charge Pumping Method to Study Distribution of Trapped Charges in SONOS Memory

In silicon-oxide-nitride-oxide-silicon （SONOS） memory and other charge trapping memories, the charge distribution after programming operation has great impact on the devic＇s characteristics,such as reading,programming/erasing, and reliability. The lateral distribution of injected charges can be measured precisely using the charge pumping method. To improve the precision of the actual measurement, a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side, respectively. Finally, the electron distribution after channel hot electron programming in SONOS memory is obtained,which is close to the drain side with a width of about 50nm.

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .

Nano watermill driven by revolving charge

A novel nanoscale watermill for the unidirectional transport of water molecules through a curved single-walled carbon nanotube（SWNT） is proposed and explored by molecular dynamics simulations. In this nanoscale system, a revolving charge is introduced to drive a water chain confined inside the SWNT, the charge and the tube together serving as a nano waterwheel and nano engine. A resonance-like phenomenon is found, and the revolving frequency of the charge plays a key role in pumping the water chain. The water flux across the SWNT increases with respect to the revolving frequency of the external charge and it reaches its maximum when the frequency is 4 THz. Correspondingly, the number of hydrogen bonds in the water chain inside the SWNT decreases dramatically as the frequency increases from 4 THz to 25 THz. The mechanism behind the resonance phenomenon has been investigated systematically. Our findings are helpful for the design of nanoscale fluidic devices and energy converters.

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。

电学计量中的量子标准与自然常数

介绍了库仑定律和安培定律在电学单位制中发挥的作用,依据机械功率与电功率等效的原理,选择电流单位安培(A)作为基本物理单位,并介绍了实用单位制和电学实物计量标准。阐述了三种电学计量的量子标准原理和溯源到自然常数的途径,分析了真空磁导率在安培定律公式中发挥的作用,探讨了电学量子三角形与欧姆定律兼容的问题。指出基本电荷量常数不是简单地从约瑟夫森常数K_(J-90)和冯·克里青常数R_(H-90)推导而来,而是由精细结构常数公式计算出来的,能量守恒原理是单位制中的第一性原理,是力学和电学计量单位的纽带。提出量子点之间的位移电流对单电子隧道泵有一定的影响,真空磁导率不再是理想的常数,真空磁导率的变化将成为后来理论界研究的重点。

适用于宽带宽的快速锁定电荷泵锁相环设计

文章基于TSMC 0.18μm CMOS工艺,设计一种适用于宽带宽下可快速锁定的电荷泵锁相环(charge pump phase-locked loop,CPPLL)。采用一种自适应快速锁定结构,比较参考信号与反馈信号的频率、相位,通过开启大电流与小电流快速锁定通路,对环路滤波器中的电容进行放电使得压控振荡器的控制电压降至锁定电平附近的方法,最大限度地减小锁定时间。通过SPECTRE仿真验证表明,在1.8 V供电电压下,输出频率为768 MHz时,锁定时间仅需1.5μs,缩短了78%,功耗为3.6 mW。

集成双频无源RFID传感器标签设计

针对超高频和高频RFID传感器由于各自测量距离和使用便捷性而导致应用场合的局限,提出一种集成超高频和高频的双频无源RFID传感器标签设计方法。首先,集成超高频和高频射频供电和数据收发模块,达到超高频和高频双频读写目的;其次,为提高双频RFID传感器标签在超高频模式下的读取距离,采用电荷泵对射频收发芯片输出电压进行升压管理以延长放电时间;然后,为增强传感器标签的通用性,将测量数据集成到高频NDEF消息和超高频用户数据段中。根据以上方法,设计了双频无源RFID温湿度传感器标签。同时搭建了实验平台对电荷泵提升读取距离的可行性和传感器标签功能进行了实验验证。实验结果表明:该传感器标签可以同时支持超高频和高频2种读取模式;使用电荷泵升压能量管理有效提升了读取距离;可通过支持EPCC1G2协议的通用超高频读写器和NFC手机方便地获取传感器测量数据。

基于电荷泵的倍增/反向双输出电压转换设计与实现

为了解决目前基于电荷泵的开关电容电压转换芯片功能较为单一的问题,基于Dickson经典电荷泵结构,匹配四路双极型晶体管开关同时实现对输入电压的倍增输出以及倍增后的电压反向。四路二极管充作开关来使用,在降低开关器件导通电压的同时简化了开关电路,缩小了电路的尺寸,并降低了电路的功耗。基于国内某工艺线的40 V互补双极型工艺,设计并制作了带正/负两路输出的开关电容电荷泵电压转换器芯片电路。流片测试结果表明:当电源电压为4 V(负载电流为0 mA、+10 mA)、5 V(负载电流为±10 mA)、9 V(负载电流为+10 mA)、10 V(负载电流为-10 mA)以及11 V(空载)时,输出电压均满足设计指标。

电力市场环境下抽水蓄能电站容量电费定价与成本分摊方法

抽水蓄能电站作为一种有效的电力系统灵活性资源,将成为保障新型电力系统安全稳定运行的重要手段。制定合理的回收抽水蓄能电站建设固定成本方案是支撑系统运行、激励投资的关键问题。在抽水蓄能电站的市场化运行背景下,构建了抽水蓄能电站顺次参与现货-辅助服务市场的容量电费定价模型,实现以经营期内收支平衡为目标定期滚动核定抽水蓄能电站的待分摊成本。同时,考虑抽水蓄能电站容量电费的潜在分摊对象,提出采用效用比例VCG(Vickrey-Clarke-Groves)机制对抽水蓄能电站容量电费进行成本分摊,量化源荷侧分摊主体的替代效益,并将容量电费按比例分摊。实际系统算例的仿真分析验证了所提方法的有效性。

适用于Flash型FPGA的宽范围输出负压电荷泵设计

在Flash型FPGA的编程、擦除和回读检验等操作中,需要对Flash单元提供不同的正负高压偏置。提出一种适用于Flash型FPGA的负压电荷泵,该电荷泵采用三阱Flash工艺,消除了衬偏效应和衬底漏电的影响。电荷泵主体采用双支路并联结构,级数为6级。通过参考电压产生电路提供不同的输入参考电压,并结合电荷泵控制系统,可以实现电荷泵输出电压的自由调节,满足Flash型FPGA编程、擦除的负压要求。基于0.13μm Flash工艺对电荷泵进行设计及流片,在200 pF负载电容下,实测得到-5.5 V输出的建立时间仅为8μs,输出纹波为72 mV,-17.5 V输出的建立时间为30μs,输出纹波仅为56 mV,满足Flash型FPGA操作要求。