Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Small Area ROM Design for Embedded Applications

The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.

An asymmetrical sensing scheme for 1T1C FRAM to increase the sense margin

A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed,in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier.Compared with the conventional symmetrical scheme in Ref.[8],the proposed scheme increases the sense margin of the readout current by 53.9%and decreases the sensing power consumption by 14.1%,at the cost of an additional 7.89%area of the sensing scheme.An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35μm three metal process,in which the function of the prototype is verified.

Design of a reliable PUF circuit based on R–2R ladder digital-to-analog convertor

A novel physical unclonable functions （PUF） circuit is proposed, which relies on non-linear characteristic of analog voltage generated by R-2R ladder DAC. After amplifying the deviation signal, the robustness of the DAC-PUF circuit has increased significantly. The DAC-PUF circuit is designed in TSMC 65 nm CMOS technology and the layout occupies 86.06 × 63.56μm^2. Monte Carlo simulation results show that the reliability of the DAC-PUF circuit is above 98% over a comprehensive range of environmental variation, such as temperature and supply voltage.