The Methodology of Testability Prediction for Sequential Circuits

Increasingly, test generation algorithms are being developed with the con-tinuous creations of incredibly sophisticated computing systems. Of all the developments of testable as well as reliable designs for computing systems, the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue. Although dozens of algorithms have been proposed to cope with this issue, it still remains much to be desired in solving such problems as to determine 1) which of the existing test generation algorithms could be the most efficientfor some particular circuits (by efficiency, we mean the Fault Coverage the algorithm offers, CPU time when executing, the number of test patterns to be applied, etc.) since different algorithms would be preferable for different circuits;2) which parameters (such as the number of gates, flip-flops and loops, etc.,in the circuit) will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.Testability forecasting methodology for the sequential circuits using regres-sion models is presented which a user usually needs for analyzing his own circuits and selecting the most suitable test generation algorithm from all possible al-gorithms available. Some examples and experiment results are also provided in order to show how helpful and practical the method is.

Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

An Efficient Method for Behavioral RTL ATPG

The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.

Tribotronic triggers and sequential logic circuits

In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.

Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA's inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.