Fabrication and Characterization of Strained Si Material Using SiGe Virtual Substrate for High Mobility Devices

The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET's ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.

Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates

Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.

A strained Si-channel NMOSFET with low field mobility enhancement of about 140% using a SiGe virtual substrate

A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a SiGe virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics.

Fabrication of High Quality SiGe Virtual Substrates by Combining Misfit Strain and Point Defect Techniques

High quality strain-relaxed thin SiGe virtual substrates have been achieved by combining the misfit strain technique and the point defect technique. The point defects were first injected into the coherently strained SiGe layer through the ＂inserted Si layer＂ by argon ion implantation. After thermal annealing, an in- termediate SiGe layer was grown with a strained Si cap layer. The inserted Si layer in the SiGe film serves as the source of the misfit strain and prevents the threading dislocations from propagating into the next epitaxial layer. A strained-SilSiGelinserted-SilSiGe heterostructure was achieved with a threading dislocation density of 1×10^4 cm-2 and a root mean square surface roughness of 0.87 nm. This combined method can effectively fabricate device-quality SiGe virtual substrates with a low threading dislocation density and a smooth surface.

Fabrication of strained Ge film using a thin SiGe virtual substrate

This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs,we present a method to prepare strained-Si material with highquality surface and ultra-thin SiGe virtual substrate.By sandwiching a low-temperature Si（LT-Si） layer between a Si buffer and a pseudomorphic Si_（0.8）Ge_（0.2） layer,the surface roughness root mean square（RMS） is 1.02 nm and the defect density is 10~6 cm^（-2） owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si_（0.8）Ge_（0.2） layer.By employing P~＋ implantation and rapid thermal annealing, the strain relaxation degree of the Si_（0.8）Ge_（0.2） layer increases from 85.09%to 96.41%and relaxation is more uniform. Meanwhile,the RMS（1.1nm） varies a little and the defect density varies little.According to the results,the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.