Design and Fabrication of Thermo-Optic 4×4 Switching Matrix in Silicon-on-Insulator

A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between -12 and -19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.

Fabrication and Evaluation of Bragg Gratings on Optimally Designed Silicon-on-Insulator Rib Waveguides Using Electron-Beam Lithography

The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental and theoretical evaluations of the Bragg grating are demonstrated. By thinning the SOl device layer and deeply etching the Bragg grating, a large grating coupling coefficient of 30cm^-1 is obtained.

Design and Fabrication of Ultracompact 3-dB MMI Coupler in Silicon-on-Insulator

An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is ～40% shorter in length.The device exhibits uniformity of 1 3dB and excess loss of 2 5dB.

SOI晶体管和电路的瞬时电离辐射效应研究

基于全介质隔离的绝缘硅(Silicon-on-insulator,SOI)器件与体硅器件的瞬时电离辐射效应存在差异,采用1 064 nm/12 ns激光装置开展了三种SOI晶体管的激光辐照试验,测试了不同激光能量下的晶体管光电流;采用脉冲γ射线辐射源开展了SOI集成电路的瞬时γ剂量率辐射试验,测试了不同剂量率条件下的电路功能、电参数和触发器链状态。研究表明:在相同激光能量条件和相同特征尺寸条件下,SOI晶体管的光电流峰值约为体硅晶体管的3.5%;SOI集成电路在1.0×10^(9)~4.2×10^(11) rad(Si)·s^(-1)的试验剂量率范围内无闭锁效应,但存在显著的翻转效应,表现为功能短暂中断、电流和电压波动以及大量触发器状态错误。翻转效应的主要原因包括晶体管本身的翻转和印刷电路板(Printed Circuit Board,PCB)板级电路的电压波动。

一种注入增强型快速SOI-LIGBT新结构研究

薄顶层硅SOI(Silicon on Insulator)横向绝缘栅双极型晶体管(Lateral Insulated-Gate Bipolar Transistor, LIGBT)的正向饱和电压较高,引入旨在减小关断态拖尾电流的集电极短路结构后,正向饱和电压进一步增大。提出了一种注入增强型(Injection Enhancement, IE)快速LIGBT新结构器件(F-IE-LIGBT),并对其工作机理进行了理论分析和模拟仿真验证。该新结构F-IE-LIGBT器件整体构建在薄顶层硅SOI衬底材料上,其集电极采用注入增强结构和电势控制结构设计。器件及电路联合模拟仿真说明:新结构F-IE-LIGBT器件在获得较小正向饱和电压的同时,减小了关断拖尾电流,实现了快速关断特性。新结构F-IE-LIGBT器件非常适用于SOI基高压功率集成电路。

SOI高压LDMOS器件氧化层抗总电离剂量辐射效应研究

绝缘体上硅(SOI)高压横向扩散金属氧化物半导体(LDMOS)器件是高压集成电路的核心器件,对其进行了总电离剂量(TID)辐射效应研究。利用仿真软件研究了器件栅氧化层、场氧化层和埋氧化层辐射陷阱电荷对电场和载流子分布的调制作用,栅氧化层辐射陷阱电荷主要作用于器件沟道区,而场氧化层和埋氧化层辐射陷阱电荷则主要作用于器件漂移区;辐射陷阱电荷在器件内部感生出的镜像电荷改变了器件原有的电场和载流子分布,从而导致器件阈值电压、击穿电压和导通电阻等参数的退化。对80 V SOI高压LDMOS器件进行了总电离剂量辐射实验,结果表明在ON态和OFF态下随着辐射剂量的增加器件性能逐步衰退,当累积辐射剂量为200 krad(Si)时,器件的击穿电压大于80 V,阈值电压漂移为0.3 V,器件抗总电离剂量辐射能力大于200 krad(Si)。

Fabrication and Simulation of Silicon-on-Insulator Structure with Si_3N_4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

New Method of Total Ionizing Dose Compact Modeling in Partially Depleted Silicon-on-Insulator MOSFETs

On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.

100 V SOI厚栅氧LDMOS器件设计与优化

基于高压模拟开关需求,对100 V绝缘体上硅(SOI)厚栅氧横向扩散金属氧化物半导体(LDMOS)器件开展研究。利用仿真软件,研究了该LDMOS器件的结构参数,包括漂移区长度、漂移区掺杂剂量、多晶硅栅场板长度对LDMOS器件击穿电压的影响。采用沟道离子补偿注入的方法,通过控制沟道区调整沟道区硼离子注入剂量,调节器件的阈值电压,同时通过优化N阱区(N-well)注入窗口长度改善器件的饱和电流。

基于0.15μm SOI工艺的耐高温短沟器件设计与实现

绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。

图形化Silicon-on-Insulator衬底上分子束外延生长可动GaN微光栅的研究

GaN材料作为第三代半导体材料,具有宽禁带、直接带隙、耐腐蚀等优点,是一种非常有前景的MOEMS材料。由于GaN的刻蚀目前尚未成熟,因此图形化外延生长法是一种较好的选择。本文基于SOI(silicon-on-insulator)基片,利用硅的微加工技术和图形化GaN分子束外延生长工艺,设计并加工了工作在太赫兹波段的、可以在二维方向上运动的SOI基GaN光栅。光栅周期为16μm,光栅宽度为6μm,峰值位置为25.901μm。通过仿真优化,设计的微驱动器在水平电压220V时,水平方向上的位移为±7.26μm;垂直方向加200V电压时,垂直位移2.5μm。为了研究在图形化SOI衬底上外延生长的InGaN/GaN量子阱薄膜的光学性能,用激光拉曼光谱仪对薄膜进行了光致发光光谱实验。实验结果表明,InGaN/GaN量子阱薄膜具有良好的发光性能,其发光范围为350~500nm,覆盖了紫外光到黄绿光。由于局域态效应与禁带收缩的作用,随着环境温度由10K升高至室温,薄膜的PL光谱的峰位呈现"S"形变化趋势。

Study on the defect-related emissions in the light self-ion-implanted Si films by a silicon-on-insulator structure

This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After the suitable annealing, these samples are characterized by using the photoluminescence technique at different recorded temperatures. Plentiful emission peaks are observed in these implanted silicon-on-insulator samples, including the unwonted intense P~ band which exhibits a great potential in the optoelectronic application. These results indicate that severe transformation of the interstitial clusters can be manipulated by the implanting dose at suitable annealing temperatures. The high critical temperatures for the photoluminescence intensity growth of the two signatures are well discussed based on the thermal ionization model of free exciton.

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

A comparative study of YBa_2Cu_3O_(7-δ)/YSZ bilayer films deposited on silicon-on-insulator substrates with and without HF pretreatment

Highly epitaxial YBa2Cu3O7-δ （YBCO） and yttria-stabilized zirconia （YSZ） bilayer thin films have been deposited on silicon-on-insulator （SOI） substrates by using in situ pulsed laser deposition （PLD） technique. In the experiment, the native amorphous SiO2 layers on some of the SOI substrates are removed by dipping them in a 10% HF solution for 15 s. Comparing several qualities of films grown on substrates with or without HF pretreatment, such as thin film crystallinity, general surface roughness, temperature dependence of resistance, surface morphology, as well as average crack spacing and crack width, naturally leads to the conclusion that preserving the native SiO2 layer on the surface of the SOI substrate can not only simplify the experimental process but can also achieve fairly high quality YSZ and YBCO thin films.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

Total dose radiation response of modified commercial silicon-on-insulator materials with nitrogen implanted buried oxide

Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad（SiO2）. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.

Influence of nitrogen implantation into the buried oxide on the radiation hardness of silicon-on-insulator wafers

In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.

An analytical model for coplanar waveguide on silicon-on-insulator substrate with conformal mapping technique

In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacitance and the conductance of the sandwich substrate. The validity of the model is verified by the full-wave method and the experimental data. It is found that the inductance, the resistance, the capacitance and the conductance from the analytical model show they are in good agreement with the corresponding values extracted from experimental Sparameter until 10 GHz.