Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an ...Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an available countermeasure based on randomization is proposed in this paper. Time delay is inserted in the operation process and random number is precharged to the circuit during the delay time,the normal schedule is disturbed and the power is randomized. Following this meth-odology,a general DPA resistance random precharge architecture is proposed and DES algorithm following this architecture is implemented. This countermeasure is testified to be efficient to resist DPA.展开更多
Leakage power analysis(LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static(leakage) power. This novel power analysis attacks take advantage of the dependence of the lea...Leakage power analysis(LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static(leakage) power. This novel power analysis attacks take advantage of the dependence of the leakage power of complementary metal oxide semiconductor(CMOS) integrated circuits on the data they process. This paper proposes symmetric dual-rail logic(SDRL), a standard cell LPA attack countermeasure that theoretically resists the LPA attacks. The technique combines standard building blocks to make new compound standard cells, which are close to constant leakage power consumption. Experiment results show SDRL is a promising approach to implement an LPA-resistant crypto processor.展开更多
在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的...在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.展开更多
This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs...This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs to differentiate power traces to the maximal probability. A simulation-based AES ASIC implementation and experimental platform are built. Various power attacks are conducted on our AES hardware implementation. Unlike on software implementations, conventional power attacks on hardware implementations may not succeed or require more computations. However, the method we proposed effectively improves the success rate using acceptable number of power traces and fewer computations. Furthermore from experimental data, the correlation factor between the hamming distance of key guesses and the difference of DPA traces has the value 0.9233 to validate power model and attack results.展开更多
文摘Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an available countermeasure based on randomization is proposed in this paper. Time delay is inserted in the operation process and random number is precharged to the circuit during the delay time,the normal schedule is disturbed and the power is randomized. Following this meth-odology,a general DPA resistance random precharge architecture is proposed and DES algorithm following this architecture is implemented. This countermeasure is testified to be efficient to resist DPA.
基金the Software and Integrated CircuitIndustries Development Foundation of Shanghai(No.12Z116010001)
文摘Leakage power analysis(LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static(leakage) power. This novel power analysis attacks take advantage of the dependence of the leakage power of complementary metal oxide semiconductor(CMOS) integrated circuits on the data they process. This paper proposes symmetric dual-rail logic(SDRL), a standard cell LPA attack countermeasure that theoretically resists the LPA attacks. The technique combines standard building blocks to make new compound standard cells, which are close to constant leakage power consumption. Experiment results show SDRL is a promising approach to implement an LPA-resistant crypto processor.
文摘在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.
文摘This paper presents an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as power mode. It arranges plaintext inputs to differentiate power traces to the maximal probability. A simulation-based AES ASIC implementation and experimental platform are built. Various power attacks are conducted on our AES hardware implementation. Unlike on software implementations, conventional power attacks on hardware implementations may not succeed or require more computations. However, the method we proposed effectively improves the success rate using acceptable number of power traces and fewer computations. Furthermore from experimental data, the correlation factor between the hamming distance of key guesses and the difference of DPA traces has the value 0.9233 to validate power model and attack results.
