Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range

The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(LET) range.The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6 T SRAM or radiation-hardened double dual interlocked cells(DICE) SRAM.When the LET value is lower than the LET threshold of MCU,the SEU only manifests single cell upset,the SEU cross section increases with the decrease of voltage.The lower the LET value,the higher the SEU sensitivity to the voltage variation is.Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU.Moreover,the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range.With further scaling the feature size of devices down,it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf(COTS) SRAM.

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

Recovery of single event upset in advanced complementary metal-oxide semiconductor static random access memory cells

Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer （LET） threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal-oxide-semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology,the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated.It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing,which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design.Additionally,the effect of supply voltage on charge collection is also investigated.It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor（BJT） and the existence of the source plays an important role in supply voltage variation.

Impact of energy straggle on proton-induced single event upset test in a 65-nm SRAM cell

This paper presents a simulation study of the impact of energy straggle on a proton-induced single event upset （SEU） test in a commercial 65-nm static random access memory cell. The simulation results indicate that the SEU cross sections for low energy protons are significantly underestimated due to the use of degraders in the SEU test. In contrast, using degraders in a high energy proton test may cause the overestimation of the SEU cross sections. The results are confirmed by the experimental data and the impact of energy straggle on the SEU cross section needs to be taken into account when conducting a proton-induced SEU test in a nanodevice using degraders.

Pattern dependence in synergistic effects of total dose on single-event upset hardness

The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.

Neutron-induced single event upset simulation in Geant4 for three-dimensional die-stacked SRAM

Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevitably by neutrons.In this paper,a 3D die-stacked SRAM device is constructed based on a real planar SRAM device.Then,the single event upsets(SEUs)caused by neutrons with different energies are studied by the Monte Carlo method.The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV.The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent,but the specific values are different.The SEU cross-section is shown to be dependent on the threshold of linear energy transfer(LETth)and thickness of the sensitive volume(Tsv).The secondary particle distribution and energy deposition are analyzed,and the internal mechanism that is responsible for this difference is illustrated.Besides,the ratio and patterns of multiple bit upset(MBU)caused by neutrons with different energies are also presented.This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.

Simulation of temporal characteristics of ion-velocity susceptibility to single event upset effect

Using a Monte Carlo simulation tool of the multi-functional package for SEEs Analysis （MUFPSA）, we study the temporal characteristics of ion-velocity susceptibility to the single event upset （SEU） effect, including the deposited energy, traversed time within the device, and profile of the current pulse. The results show that the averaged dposited energy decreases with the increase of the ion-velocity, and incident ions of 2~9Bi have a wider distribution of energy deposition than 132Xe at the same ion-velocity. Additionally, the traversed time presents an obvious decreasing trend with the increase of ion-velocity. Concurrently, ion-velocity certainly has an influence on the current pulse and then it presents a particular regularity. The detailed discussion is conducted to estimate the relevant linear energy transfer （LET） of incident ions and the SEU cross section of the testing device from experiment and simulation and to critically consider the metric of LET.

Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

Synergistic effects of the total ionizing dose （TID） on the single event upset （SEU） sensitivity in static random access memories （SRAMs） were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor can mitigate the cross section of single event upset(SEU)in 14-nm complementary metal-oxide semiconductor(CMOS)bulk Fin FET technology.The competition of charge collection between well boundary and sensitive nodes,the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section.Unlike dualinterlock cell(DICE)design,this approach is more effective under heavy ion irradiation of higher LET,in the presence of enough taps to ensure the rapid recovery of well potential.Besides,the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Ionizing radiation effect on single event upset sensitivity of ferroelectric random access memory

The impact of ionizing radiation effect on single event upset（SEU） sensitivity of ferroelectric random access memory（FRAM） is studied in this work. The test specimens were firstly subjected to ^60Co γ-ray and then the SEU evaluation was conducted using ^209Bi ions. As a result of TID-induced fatigue-like and imprint-like phenomena of the ferroelectric material, the SEU cross sections of the post-irradiated devices shift substantially. Different trends of SEU cross section with elevated dose were also found, depending on whether the same or complementary test pattern was employed during the TID exposure and the SEU measurement.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.

Fault Tolerant Reconfigurable System with Dual-Module Redundancy and Dynamic Reconfiguration

To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.

Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications

Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA

According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.