Influence of Temperature on Stacking Fault Energy and Creep Mechanism of a Single Crystal Nickel-based Superalloy

The influence of temperatures on the stacking fault energies and deformation mechanism of a Re- containing single crystal nickel-based superalloy during creep at elevated temperatures was investigated by means of calculating the stacking fault energy of alloy, measuring creep properties and performing contrast analysis of dislocation configuration. The results show that the alloy at 760 ℃ possesses lower stacking fault energy, and the stacking fault of alloy increases with increasing temperature. The defor- mation mechanism of alloy during creep at 760 ℃ is 7＇ phase sheared by 〈110〉 super-dislocations, which may be decomposed to form the configuration of Shockley partials plus super-lattice intrinsic stacking fault, while the deformation mechanism of alloy during creep at 1070 ℃ is the screw or edge super- dislocations shearing into the rafted 7＇ phase. But during creep at 7（50 and 980 ℃, some super- dislocations shearing into 7＇ phase may cross-slip from the {111} to {100} planes to form the K-W locks with non-plane core structure, which may restrain the dislocations slipping to enhance the creep resis- tance of alloy at high temperature. The interaction between the Re and other elements may decrease the diffusion rate of atoms to improve the microstructure stability, which is thought to be the main reason why the K-W locks are to be kept in the Re-containing superalloy during creep at 980 ℃.

Stacking fault energy in some single crystals

The stacking fault energy of single crystals has been reported using the peak shift method.Presently studied all single crystals are grown by using a direct vapor transport（DVT） technique in the laboratory.The structural characterizations of these crystals are made by XRD.Considerable variations are shown in deformation （α） and growth（β） probabilities in single crystals due to off-stoichiometry,which possesses the stacking fault in the single crystal.

An advanced SEU tolerant latch based on error detection

This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the C-element.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5%less energy and 33.1%less propagation delay than the triple modular redundancy（TMR）latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.