This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture...This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.展开更多
文摘This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.
