The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main ...The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.展开更多
DFM （Design-For-Manufacturability） method, which aims to improve manufacturability of ICs through specific design considerations, is becoming important nowadays. In particular, standard cells now should be designed ...DFM （Design-For-Manufacturability） method, which aims to improve manufacturability of ICs through specific design considerations, is becoming important nowadays. In particular, standard cells now should be designed by DFM method. This paper reports a new DFM flow for sub-100 nm standard cell design with a group of technologies for process modeling, manufacturability simulation and trial RETs. Based on this flow, a set of DFM-friendly 90nm standard cells were designed.展开更多
Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalizatio...Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.展开更多
A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement a...A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do.An integer programming problem is formulated to minimize the adjustment on the initial placement and a heuristic method is presented to search for a shifting path so as to optimize the wirelength.Test of W ECOP on a group of practical test cases shows that the algorithm can successfully accomplish incremental placement with good quality and high speed.展开更多
This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for larg...This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.展开更多
With shrinking transistor feature size,the fin-type field-effect transistor（FinFET） has become the most promising option in low-power circuit design due to its superior capability to suppress leakage.To support the ...With shrinking transistor feature size,the fin-type field-effect transistor（FinFET） has become the most promising option in low-power circuit design due to its superior capability to suppress leakage.To support the VLSI digital system flow based on logic synthesis,we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell.This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis.The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell.For comparison,a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated.Experimental results show that the optimized cells achieve standard deviation reduction of 39.1%and 30.7%at most in worst-case delay and inputdependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage canbe up to 98.37%and 24.13%,respectively,which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.展开更多
This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common inp...This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.展开更多
China’s first general standard for stem cells officially released on November 22,2017 is expected to lay a foundation for regulating the application of stem cells technology.Stem cells are a group of self-renewal cel...China’s first general standard for stem cells officially released on November 22,2017 is expected to lay a foundation for regulating the application of stem cells technology.Stem cells are a group of self-renewal cells that can differentiate into specialized cells.They are now used for the treatment of many diseases.Despite a series of documents for regulating basic research and achievement transformation of stem cells,展开更多
基金The National Natural Science Foundation of China(No60472057)
文摘The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
文摘DFM （Design-For-Manufacturability） method, which aims to improve manufacturability of ICs through specific design considerations, is becoming important nowadays. In particular, standard cells now should be designed by DFM method. This paper reports a new DFM flow for sub-100 nm standard cell design with a group of technologies for process modeling, manufacturability simulation and trial RETs. Based on this flow, a set of DFM-friendly 90nm standard cells were designed.
文摘Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.
文摘A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do.An integer programming problem is formulated to minimize the adjustment on the initial placement and a heuristic method is presented to search for a shifting path so as to optimize the wirelength.Test of W ECOP on a group of practical test cases shows that the algorithm can successfully accomplish incremental placement with good quality and high speed.
基金supported by the National Major Specialized Program of China(Nos.2008ZX01035-001-07,2009ZX02023-4-2)
文摘This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.
基金Project supported by the National Natural Science Foundation of China(No.61306040)the State Key Development Program for Basic Research of China(No.2015CB057201)+1 种基金the Beijing Natural Science Foundation(No.4152020)Natural Science Foundation of Guangdong Province,China(No.2015A030313147)
文摘With shrinking transistor feature size,the fin-type field-effect transistor（FinFET） has become the most promising option in low-power circuit design due to its superior capability to suppress leakage.To support the VLSI digital system flow based on logic synthesis,we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell.This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis.The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell.For comparison,a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated.Experimental results show that the optimized cells achieve standard deviation reduction of 39.1%and 30.7%at most in worst-case delay and inputdependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage canbe up to 98.37%and 24.13%,respectively,which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.
文摘This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.
文摘China’s first general standard for stem cells officially released on November 22,2017 is expected to lay a foundation for regulating the application of stem cells technology.Stem cells are a group of self-renewal cells that can differentiate into specialized cells.They are now used for the treatment of many diseases.Despite a series of documents for regulating basic research and achievement transformation of stem cells,
