The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
This study describes the seismic performance of an existing five storey reinforced concrete building which represents the typical properties of low-rise non-ductile buildings in Turkey. The effectiveness of shear wall...This study describes the seismic performance of an existing five storey reinforced concrete building which represents the typical properties of low-rise non-ductile buildings in Turkey. The effectiveness of shear walls and the steel bracings in retrofitting the building was examined through nonlinear static and dynamic analyses. By using the nonlinear static analysis, retrofitted buildings seismic performances under lateral seismic load were compared with each other. Moreover, the performance points and response levels of the existing and retrofitting cases were determined by way of the capacity-spectrum method described in ATC-40 (1996). For the nonlinear dynamic analysis the records were selected to represent wide ranges of duration and frequency content. Considering the change in the stiffness and the energy dissipation capacities, the performance of the existing and retrofitted buildings were evaluated in terms of story drifts and damage states. It was found that each earthquake record exhibited its own peculiarities, dictated by frequency content, duration, sequence of peaks and their amplitude. The seismic performance of retrofitted buildings resulted in lower displacements and higher energy dissipation capacity depending mainly on the properties of the ground motions and the retrofitting strategies. Moreover, severe structural damage (irreparable or collapse) was observed for the existing building. However, buildings with retrofit alternatives exhibited lower damage levels changing from no damage to irreparable damage states.展开更多
Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,c...Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic circuits.The amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design time.In this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI degradation.It consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability distributions.This method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.展开更多
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
文摘This study describes the seismic performance of an existing five storey reinforced concrete building which represents the typical properties of low-rise non-ductile buildings in Turkey. The effectiveness of shear walls and the steel bracings in retrofitting the building was examined through nonlinear static and dynamic analyses. By using the nonlinear static analysis, retrofitted buildings seismic performances under lateral seismic load were compared with each other. Moreover, the performance points and response levels of the existing and retrofitting cases were determined by way of the capacity-spectrum method described in ATC-40 (1996). For the nonlinear dynamic analysis the records were selected to represent wide ranges of duration and frequency content. Considering the change in the stiffness and the energy dissipation capacities, the performance of the existing and retrofitted buildings were evaluated in terms of story drifts and damage states. It was found that each earthquake record exhibited its own peculiarities, dictated by frequency content, duration, sequence of peaks and their amplitude. The seismic performance of retrofitted buildings resulted in lower displacements and higher energy dissipation capacity depending mainly on the properties of the ground motions and the retrofitting strategies. Moreover, severe structural damage (irreparable or collapse) was observed for the existing building. However, buildings with retrofit alternatives exhibited lower damage levels changing from no damage to irreparable damage states.
基金3the High Performance Computing Center of Shanghai University,Shanghai Engineering Research Center of Intelligent Computing System(19DZ2252600)supported by State Key Laboratory of Computer Architecture(Institute of Computing Technology,Chinese Academy of Sciences)(CARCH201909)。
文摘Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic circuits.The amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design time.In this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI degradation.It consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability distributions.This method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.
