Waiting times and stopping probabilities for patterns in Markov chains

Suppose that C is a finite collection of patterns. Observe a Markov chain until one of the patterns in C occurs as a run. This time is denoted by τ. In this paper, we aim to give an easy way to calculate the mean waiting time E(τ) and the stopping probabilities P(τ = τA)with A ∈ C, where τA is the waiting time until the pattern A appears as a run.

Stopping time of a one-dimensional bounded quantum walk

The stopping time of a one-dimensional bounded classical random walk（RW） is defined as the number of steps taken by a random walker to arrive at a fixed boundary for the first time.A quantum walk（QW） is a non-trivial generalization of RW,and has attracted a great deal of interest from researchers working in quantum physics and quantum information.In this paper,we develop a method to calculate the stopping time for a one-dimensional QW.Using our method,we further compare the properties of stopping time for QW and RW.We find that the mean value of the stopping time is the same for both of these problems.However,for short times,the probability for a walker performing a QW to arrive at the boundary is larger than that for a RW.This means that,although the mean stopping time of a quantum and classical walker are the same,the quantum walker has a greater probability of arriving at the boundary earlier than the classical walker.

Probability stopping criterion for analog decoding of LDPC codes

To detect uncorrectable frames and terminate the decoding procedure early, a probability stopping criterion for iterative analog decoding of low density parity check （LDPC） codes is proposed in this paper. By using probabilities of satisfied checks to detect uncorrectable frames and terminate decoding, the proposed criterion could be applied to analog decoders without much structure modifications. Simulation results show that the proposed criterion can reduce the average number of iterations and achieve a better balance in bit error ratio （BER） performance and decoding complexity than other stopping criteria using extrinsic information.

Design of a(480,240)CMOS Analog Low-Density Parity-Check Decoder

Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.