AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment pr...AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment protocol in diabetic macuiar edema（DME）.METHODS：A comprehensive literature search using the Cochrane Collaboration methodology to identify RCTs comparing SDM with mETDRS for DME.The participants were type Ⅰ or type Ⅱ diabetes mellitus with clinically significant macuiar edema treated by SDM from previously reported randomized controlled trials（RCTs）.The primary outcome measures were the changes in the best corrected visual acuity（BCVA） and the central macuiar thickness（CMT） as measured by optical coherence tomography（OCT）.The secondary outcomes were the contrast sensitivity and the damages of the retina.RESULTS：Seven studies were identified and analyzed for comparing SDM（215 eyes） with mETDRS（210 eyes）for DME.There were no statistical differences in the BCVA after treatment between the SDM and mETDRS based on the follow-up：3mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.77）,6mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.75）,12mo（MD,-0.05;95% Cl,-0.17 to 0.07;P=0.40）.Likewise,there were no statistical differences in the CMT after treatment between the SDM and mETDRS in 3mo（MD,-9.92;95% Cl,-28.69 to 8.85;P=0.30）,6mo（MD,-11.37;95% Cl,-29.65 to 6.91;P=0.22）,12mo（MD,8.44;95% Cl,-29.89 to 46.77;P=0.67）.Three RCTs suggested that SDM laser results in good preservation of contrast sensitivity as mETDRS,in two different followup evaluations：3mo（MD,0.05;95% Cl,0 to 0.09;P=0.04） and 6mo（MD,0.02;95% Cl,-0.10 to 0.14;P=0.78）.Two RCTs showed that the SDM laser treatment did less retinal damage than that mETDRS did（OR,0.05;95% Cl,0.02 to 0.13;P〈0.01）.CONCLUSION：SDM laser photocoagulation shows an equally good effect on visual acuity,contrast sensitivity,and reduction of DME as compared to conventional mETDRS protocol with less retinal damage.展开更多
Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the c...Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.展开更多
Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel...Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.展开更多
A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabr...A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm^2.展开更多
The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several...The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.展开更多
This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61...This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61 amorphous silicon thin-film transistor model in star-HSPICE, the results from our equivalent circuit model simulation reveal that zero-current point dispersion can be attributed to two factors： large contact resistance and small gate resistance. Furthermore, it is found that decreasing the contact resistance and increasing the gate resistance can efficiently reduce the dispersion. If the contact resistance can be controlled to 0 g2, all the zero-current points can gather together at the base point. A large gate resistance is good for constraining the dispersion of the zero-current points and gate leakage. The variances of the zero-current points are 0.0057 and nearly 0 when the gate resistances are 17 MΩ and 276 MΩ, respectively.展开更多
This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the...This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW,dynamic power of 385 nW @ 165 kHz,EDP 13 pJ/inst and the operating voltage of 350 mV are achieved.Under a light of about 150 kLux,the microprocessor can run at a rate of up to 500 kHz.The microprocessor can be used for wireless-sensor-network nodes展开更多
This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the ch...This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.展开更多
A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface pote...A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.展开更多
A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are pre...A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are presented. Being different from traditional techniques, this idea focuses on finding multiple temperatures in the whole range at which the first order derivatives of the output reference voltage equal zero. In this way, the curve of the output reference voltage is flattened and a better effect of curvature compensation is achieved. The circuitry is simulated in ST Microelectronics 0. 18μm CMOS technology, and the simulated result shows that the average temperature coefficient is only 1ppm/℃ in the range from - 40 to 125℃.展开更多
分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为...分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为线性区MOS管提供偏压以进一步降低功耗。基于SMIC 0.18μm CMOS工艺设计电路。仿真结果表明此电路在1.8 V电源电压下,–50^+150℃的温度系数为22.6×10–6/℃,基准电压源输出电压约为992 m V,25℃时静态电流为327.3 n A,电路总静态功耗为0.59μW,10 k Hz时的电源抑制比为–25.36 d B。展开更多
文摘AIM：To examine possible differences in clinical outcomes between sub-threshold micro-pulse diode laser photocoagulation（SDM） and traditional modified Early Treatment Diabetic Retinopathy Study（mETDRS）treatment protocol in diabetic macuiar edema（DME）.METHODS：A comprehensive literature search using the Cochrane Collaboration methodology to identify RCTs comparing SDM with mETDRS for DME.The participants were type Ⅰ or type Ⅱ diabetes mellitus with clinically significant macuiar edema treated by SDM from previously reported randomized controlled trials（RCTs）.The primary outcome measures were the changes in the best corrected visual acuity（BCVA） and the central macuiar thickness（CMT） as measured by optical coherence tomography（OCT）.The secondary outcomes were the contrast sensitivity and the damages of the retina.RESULTS：Seven studies were identified and analyzed for comparing SDM（215 eyes） with mETDRS（210 eyes）for DME.There were no statistical differences in the BCVA after treatment between the SDM and mETDRS based on the follow-up：3mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.77）,6mo（MD,-0.02;95% Cl,-0.12 to 0.09;P=0.75）,12mo（MD,-0.05;95% Cl,-0.17 to 0.07;P=0.40）.Likewise,there were no statistical differences in the CMT after treatment between the SDM and mETDRS in 3mo（MD,-9.92;95% Cl,-28.69 to 8.85;P=0.30）,6mo（MD,-11.37;95% Cl,-29.65 to 6.91;P=0.22）,12mo（MD,8.44;95% Cl,-29.89 to 46.77;P=0.67）.Three RCTs suggested that SDM laser results in good preservation of contrast sensitivity as mETDRS,in two different followup evaluations：3mo（MD,0.05;95% Cl,0 to 0.09;P=0.04） and 6mo（MD,0.02;95% Cl,-0.10 to 0.14;P=0.78）.Two RCTs showed that the SDM laser treatment did less retinal damage than that mETDRS did（OR,0.05;95% Cl,0.02 to 0.13;P〈0.01）.CONCLUSION：SDM laser photocoagulation shows an equally good effect on visual acuity,contrast sensitivity,and reduction of DME as compared to conventional mETDRS protocol with less retinal damage.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2
文摘Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.
文摘Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.
文摘A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm^2.
基金supported by the Hi-Tech Research and Development Program of China(No.2009AA01Z114)
文摘The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.
文摘This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61 amorphous silicon thin-film transistor model in star-HSPICE, the results from our equivalent circuit model simulation reveal that zero-current point dispersion can be attributed to two factors： large contact resistance and small gate resistance. Furthermore, it is found that decreasing the contact resistance and increasing the gate resistance can efficiently reduce the dispersion. If the contact resistance can be controlled to 0 g2, all the zero-current points can gather together at the base point. A large gate resistance is good for constraining the dispersion of the zero-current points and gate leakage. The variances of the zero-current points are 0.0057 and nearly 0 when the gate resistances are 17 MΩ and 276 MΩ, respectively.
基金Project supported by the National Natural Science Foundation of China(No.60906010)
文摘This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW,dynamic power of 385 nW @ 165 kHz,EDP 13 pJ/inst and the operating voltage of 350 mV are achieved.Under a light of about 150 kLux,the microprocessor can run at a rate of up to 500 kHz.The microprocessor can be used for wireless-sensor-network nodes
基金Project supported by the National Natural Science Foundation of China(No.60906010).
文摘This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.
文摘A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.
文摘A new method,namely multiple point curvature compensation （MPCC）,is proposed for the design of a bandgap reference,and its design principles, theoretical derivation, and one feasible circuitry implementation are presented. Being different from traditional techniques, this idea focuses on finding multiple temperatures in the whole range at which the first order derivatives of the output reference voltage equal zero. In this way, the curve of the output reference voltage is flattened and a better effect of curvature compensation is achieved. The circuitry is simulated in ST Microelectronics 0. 18μm CMOS technology, and the simulated result shows that the average temperature coefficient is only 1ppm/℃ in the range from - 40 to 125℃.
文摘分析了工作在亚阈值区、线性区和饱和区的MOS晶体管不同电流特性,设计了一种低功耗全MOS基准电压源电路。使用工作在线性区的MOS晶体管代替普通常规电阻,使整个电路实现全MOS基准源的特性,同时有效减小电路芯片面积,并且输出基准电压为线性区MOS管提供偏压以进一步降低功耗。基于SMIC 0.18μm CMOS工艺设计电路。仿真结果表明此电路在1.8 V电源电压下,–50^+150℃的温度系数为22.6×10–6/℃,基准电压源输出电压约为992 m V,25℃时静态电流为327.3 n A,电路总静态功耗为0.59μW,10 k Hz时的电源抑制比为–25.36 d B。
