Correction of microwave pulse reflection by digital filters in superconducting quantum circuits

Reducing the control error is vital for high-fidelity digital and analog quantum operations.In superconducting circuits,one disagreeable error arises from the reflection of microwave signals due to impedance mismatch in the control chain.Here,we demonstrate a reflection cancelation method when considering that there are two reflection nodes on the control line.We propose to generate the pre-distortion pulse by passing the envelopes of the microwave signal through digital filters,which enables real-time reflection correction when integrated into the field-programmable gate array(FPGA).We achieve a reduction of single-qubit gate infidelity from 0.67%to 0.11%after eliminating microwave reflection.Real-time correction of microwave reflection paves the way for precise control and manipulation of the qubit state and would ultimately enhance the performance of algorithms and simulations executed on quantum processors.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.

Digital synthesis of programmable photonic integrated circuits

Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.

Reconfigurable Digital Circuits Based on Chip Expander with Integrated Temperature Regulation

This article is dealing with a development of custom chip expander platform with the possibility of accurate temperature control and integration of additional silicon-based features. Such platform may serve as a useful tool which facilitates the burdens connected with measurement and analysis tasks of experimental semiconductor structures. The devised solution provides the functionality of carrier substrate (Al2O3 compound) with CTE compatibility to the experimental silicon chip and is fully customizable with respect to a particular chip. It also allows achieving an easy fan-out of small-diameter chip terminals into a larger, more convenient area and placement of chip specimens conveniently into space-constrained chamber of the AFM microscopes, probe stations, etc. Real application of the developed chip expander platform is demonstrated in context of digital reconfigurable circuits based on polymorphic electronics. In this case the chip expander with attached polymorphic chip REPOMO is thermally stabilized at an ambient temperature level up to approximately 135。C and its sensitivity to this phenomenon is demonstrated.

Digitalization of inverting filter shaping circuit for nuclear pulse signals

In the design of filter shaping circuits for nuclear pulse signals,inverting filter shaping circuits perform better than non-inverting filter shaping circuits.Because these circuits facilitate changing the phase of a pulse signal,they are widely used in processing nuclear pulse signals.In this study,the transfer functions of four types of inverting filter shaping circuits,namely the common inverting filter shaping,improved inverting filter shaping,multiple feedback low-pass filter shaping,and third-order multiple feedback low-pass filter shaping,in the Laplacian domain,are derived.We establish the numerical recursive function models and digitalize the four circuits,obtain the transfer functions in the Z domain,and analyze the filter performance and amplitude-frequency response characteristics in the frequency domain.Based on the actual nuclear pulse signal of the Si-PIN detector,we realize four types of inverting digital shaping.The results show that under the same shaping parameters,the common inverting digital shaping has better amplitude extraction characteristics,the third-order multiple feedback low-pass digital shaping has better noise suppression performance,and the multiple feedback digital shaping takes into account both pulse amplitude extraction and noise suppression performance.

Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

Application of digital driving circuit in arc welding power source based on HCPL-316J

The digitalization of arc welding power source mainly depends on the digitalization of arc welding inverter,so that main circuit and controlling system can give full play to advantages.Digital switching control makes main circuit digital and DSP and/or MCU makes controlling system,digital.So IGBT driving circuit,as a tie of main circuit and controlling system,should also be got digitalized.Thus,a digital driving circuit based on optocoupler device HCPL-316 J is provided.Some testing experiments were done.After driving testing,the driving circuit certificates that driving waveforms satisfy the requirements of arc welding power source and the driving circuit is reasonably and simply designed.And the driving circuit has high controlling precision and reliability.No-load-voltage testing and welding external characteristic testing prove that the driving circuit can be applied in arc welding power source.

Evolutionary Design of Fault-Tolerant Digital Circuit Based on Cartesian Genetic Programming

In many areas, reliability of the digital circuits has become the key factor to restrict circuit development. Fault-tolerant design is the commonly used method to improve the reliability of digital circuits. The current fault-tolerant design methods are based on triple modular redundancy( TMR) or multiple modular redundancy( MMR). These redundancy designs rely on the experience of the designers,and the designed circuits have poor adaptabilities to a complex environment. However, evolutionary design of digital circuits does not rely on prior knowledge. During the evolution, some novel and optimal circuit topologies can be found, and the evolved circuits can feature strong adaptive capacities. Based on Cartesian genetic programming( CGP), a novel method for designing fault-tolerant digital circuits by evolution is proposed,key steps of the evolution are introduced,influences of function sets on evolution are investigated,and as a preliminary result,an evolved full adder with high fault-tolerance is shown.

DIGITAL CIRCUIT MACROMODELING WITH PSPICE

Ordinary algebra is used to represent Boolean algebra on logic variables with states 0 and 1, so to achieve a unify approach to simulated both digital and analog circuit in PSPICE. Result on mixed A/D simulation shows a save in memory but generally longer run time.

Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

CircuitVerse:A Simulator for Teaching and Learning of Digital Logic Circuit

Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.

VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.

Dual DVCC Based Voltage-Mode Digitally Programmable Biquadratic Filter

The recent advances in IC technology have led to the trend of designing hybrid systems to benefit both analog and the digital domain. Among analog circuits, multifunctional filter along with multiphase oscillator constitutes a building block of critical importance. In this paper, a digitally reconfigurable multi-input-multi-output voltage mode multifunctional biquadratic filter has been presented. The circuit comprises of two differential voltage current conveyors (DVCCs), two grounded capacitors and two floating resistors. The digital controllability is incorporated using a current-summing network (CSN). Tunability of quality factor is achieved by the use of a 3-bit digital control word while keeping the resonant frequency constant. PSPICE simulations using TSMC 0.25 μm CMOS technology have been performed to validate the theoretically predicted results.

Characterization of Fundamental Logics for the Sub-Threshold Digital Design

Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.

Low Noise Amplifier Design for Digital Television Applications

The DVB-T (Digital Video Broadcasting—Terrestrial) standard is being deployed in many parts of the world for digital broadcasting services, providing a variety of features extending the capabilities of the older analog ones. In this paper, a two-stage low noise amplifier (LNA) is designed for use with the DVB-T standard. The design is employed based on microstrip. The microwave design meets all the specifications required, achieving input and output return loss below ?10 dB, high gain of 35 dB and high linearity. Low noise figure of 1.3 dB is achieved with the use of pHEMT transistor technology.

Design of Polymorphic Operators for Efficient Synthesis of Multifunctional Circuits

Systematic effort dedicated to the exploration of feasible ways how to permanently come up with even more space-efficient implementation of digital circuits based on conventional CMOS technology node may soon reach the ultimate point, which is mostly given by the constraints associated with physical scaling of fundamental electronic components. One of the possible ways of how to mitigate this problem can be recognized in deployment of multifunctional circuit elements. In addition, the polymorphic electronics paradigm, with its considerable independence on a parti- cular technology, opens a way how to fulfil this objective through the adoption of emerging semiconductor materials and advanced synthesis methods. In this paper, main attention is focused on the introduction of polymorphic operators (i.e. digital logic gates) that would allow to further increase the efficiency of multifunctional circuit synthesis techniques. Key aspect depicting the novelty of the proposed approach is primarily based on the intrinsic exploitation of components with ambi- polar conduction property. Finally, relevant models of the polymorphic operators are presented in conjunction with the experimental results.