A PARALLEL SWITCH FABRIC BASED ON CROSSBAR

With the increase of link rate, the arbitrator of centralized switch fabric becomes too complicated to implement. A parallel switch fabric based on crossbar, named as PSFBC (Parallel Switch Fabric Based on Crossbar), has been proposed in this paper. PSFBC is composed of k switches whose rate is 1/k of link', these switches exchange cells in parallel; this increases the arbitrator's period and make it easy to implement. Load is evenly distributed to each switch with FCFS (First Come First Serve) rule, it can keep the order of cells in one stream. A multi-class queue scheduling policy is used in PSFBC to ensure the quality of realtime streams. Experiments show that the load on each switch in PSFBC is well balanced, its average delay of cells is little and its performance is very close to centrali{ed switch; and with the increase of number of parallel switches, the loss of PSFBC's performance keeps very small, it becomes easier to implement.

A Load-Balanced Crosspoint-Queued Switch Fabric

The fast growth of Internet has cre-ated the need for high-speed switches. Re-cently, the crosspoint-queue switch has at-tracted attention because of its scalability and high performance. However, the Cross-point-Queue switch does not perform well under non-uniform traffic. To overcome this limitation, the Load-Balanced Cross-point-Queued switch architecture has been proposed. In this architecture, a load-balance stage is placed ahead of the Cross-point-Queued stage. The load-balance stage transforms the incoming non-uniform traffic into nearly uniform traffic at the input port of the second stage. To avoid out-of-order cells, this stage employs flow-based queues in each crosspoint buffer. Analysis and simulation results reveal that under non-uniform traffic, this new switch architecture achieves a delay performance similar to that of the Out-put-Queued switch without the need for inter- nal acceleration. In addition, its throughput is much better than that of the pure cross- point-queued switch. Finally, it can achieve the same packet loss rate as the cross- point-queue switch, while using a buffer size that is only 65% of that used by the cross- point-queue switch.

PERFORMANCE ANALYSIS OF ATM SWITCH FABRIC WITH COMBINED-INPUT/OUTPUT BUFFERING

This paper analyses the performance of the ATM switch fabric with Combined-Input/ Output Buffering(C-IOB) under two different service principles for the cells at the head of line (HOL) positions of input buffers: First Come First Service (FCFS)/Random Service(RS) for the set of HOL cells addressed to a given output port with different/same "age" (the waiting time at the HOL position) and Pure Random Service(PRS) for all HOL cells addressed to a given output port regardless of their "ages" while the Queue Loss (QL) transfer scheme is adopted for interaction between input and output buffers in the ATM switch fabric. The results obtained show that the C-IOB ATM switch fabric with PRS service policy and the QL transfer scheme is better than other buffering ATM switch fabrics.

Design and Implementation of a Fast Switch Fabric

To solve the bottleneck issue of high-speed routers and switch fabrics technology for current networks, this paper provides a detailed description of how to implement a shared-memory switch fabric for packet routers by Xilinx FPGAs. The switch fabric, coined SL64, has the notable features as follows: (1) Supporting up to 16 OC-48 line cards; (2) Guaranteeing data lossless through robust flow control; (3) Supporting up to eight priorities with one strict priority; (4) Guaranteeing QoS, high throughput and starvation free through scheduling algorithm WF2Q+; (5) Provideing programmable cell length-64 bytes, 72 bytes and 80 bytes are all available for various applications.In addition, common features such as multicast support, protocol agnostic cell based switch, CRC check for cell header and embedded shared memory are also included in our switch fabric SL64.

4×4 nonblocking optical switch fabric based on cascaded multimode interferometers

We experimentally demonstrate a 4 × 4 nonblocking silicon thermo-optic(TO) switch fabric consisting of three stages of tunable generalized Mach–Zehnder interferometers. All 24 routing states for nonblocking switching are characterized. The device's footprint is 4.6 mm × 1.0 mm. Measurements show that the worst cross talk of all switching states is-7.2 dB. The on-chip insertion loss is in the range of 3.7–13.1 dB. The average TO switching power consumption is 104.8 mW.

Wavelength Reservation Scheme with Switch Fabric Status in Distributed Mesh Optical Networks

A new wavelength reservation scheme is proposed the reconfiguration times of optical cross-connects （OXCs） for we consider the reconfiguration information of switch fabrics to mitigate the connection setup time and minimize WDM optical networks in this study. In this scheme, in the signaling protocol, which is designated as the signaling with switch fabric status （SWFS）. Distributed reservation algorithms will reserve the wavelength with minimum of reconfiguration times of OXCs along the route. Simulation results indicate that the proposed schemes with switch fabrics status have shorter setup time, lower switching ratio as well as better blocking performance than those of the traditional classic schemes. Moreover, the proposed schemes with SWFS significantly reduce the number of switch fabrics that need to be reconfigured.

An Interconnected Multi-Plane Multi-Stage Fault-Tolerant On-Board Switching Fabric

The harsh space radiation environment compromises the reliability of an on-board switching fabric by leading to cross-point and switching element(SE)faults.Different from traditional faulttolerant switching fabrics only taking crosspoint faults into account,a novel Input and Output Parallel Clos network,referred to as the(p_1,p_2)-IOPClos,is proposed to tolerate both cross-point and SE faults.In the(p_1,p_2)-IOPClos,there are p_1 and p_2 expanded parallel switching planes in the input and output stages,respectively.The multiple input/output switching planes are interconnected through the middle stage to provide multiple paths in each stage by which the network throughput can be increased remarkably.Furthermore,the network reliability of the(p_1,p_2)-IOPClos under the above both kinds of faults is analyzed.The corresponding implementation cost is also presented along with the network size.Both theoretical analysis and numerical results indicate that the(p_1,p_2)-IOPClos outperforms traditional Clos-type networks at reliability,while has less implementation cost than the multi-plane Clos network.

A CENTRAL-STAGE BUFFERED THREE-STAGE CLOS SWITCHING FABRIC AND THE SCHEDULING ALGORITHM

Current MSM switching fabric has poor performance under unbalanced traffic. This paper presents an alternative, novel Central-stage Buffered Three-stage Clos switching (CB-3Clos) fabric and proves that this fabric can emulate output queuing switch without any speedup. By analyzing the condition to satisfy the central-stage load-balance, this paper also proposes a Central-stage Load-balanced-based Distributed Scheduling algorithm (CLDS) for CB-3Clos. The results show that, compared with Concurrent Round-Robin based Dispatching (CRRD) algorithm based on MSM, CLDS algorithm has high throughput irrespective with the traffic model and better performance in mean packet delay.

PERFORMANCE ANALYSIS OF AN INPUT-BUFFERED ATM SWITCHING FABRIC WITH INDEPENDENT WINDOW-ACCESS SCHEME

In this paper, an Independent Window-Access(IWA) scheme is proposed, and the performance of an input-buffered ATM switching fabric with the IWA scheme is analysed by means of a probability generating function approach, the closed formulas of the average cell delay and the maximum throughput are given, and results show that the IWA scheme makes the switching fabric have better performances than traditional window-access scheme. The computer simulation results are in good agreement with these analytical results.

StarFabric技术综述

开关互连(Switched Fabric)技术将取代并行总线技术,成为新一代信号与信息处理机系统互连的解决方案。星型结构(StarFabric)是一种交换性能和可开发性较好的开关互连技术,用之可以较快地建立起以开关网络为中心架构的高性能信号与信息处理机系统平台。介绍了当前开关互连技术的发展现状;重点研究了StarFabric开关互连技术的互连协议、工作原理、技术特点和供开发的软硬件资源;对比分析了当前主流开关互连技术,并给出了星型结构技术的应用前景及其应用选择参考。

基于Fabric网络平台的中间件设计

基于Fabric网络拓扑及其传输特点,设计了模块级综合化信号与信息处理机的网络通信中间件模型,详细描述了其中的Fabric通信模型、网络管理模型和图形化配置监控模型。该中间件通过映射Fabric物理端口为多个逻辑通信端口,屏蔽网络链路的容错细节,以及静态逻辑连接关系和应用部署的动态绑定,实现了位置无关的网络通信、应用部署、容错控制、配置及监控维护等处理机平台基础设施,减小了系统应用与机器平台的设计耦合,增强了系统应用的设计灵活性,可以显著提高系统应用的集成效率。

一种基于StarFabric总线的通用信号处理平台设计

基于共享总线(CPCI或VME)的信号处理模块由于共享总线带宽逐渐成为提升信号处理系统性能的瓶颈,开关互连技术是新一代信号处理系统互连的趋势。给出了一种基于StarFabric总线的多DSP构成的通用信号处理平台设计,突破了这种设计瓶颈,能满足多种信号处理功能的需要。

On Some Key Technologies of ATM Switching

In this paper,the functions and the architecture of an ATM exchange are summarized.The switching fabrics,the line interface module and the control module are discussed in de-tail.An ATM switching system that adopts the scheme described in this paper has been de-veloped.

Fast and Noniterative Scheduling in Input-Queued Switches

Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling system such as iSLIP. Iterative schedulers are not very scalable and can be slow. We propose a new scheduling algorithm that finds a maximum matching of a modified I/O mapping graph in a single iteration (hence noniterative). Analytically and experimentally, we show that it provides full throughput and incurs very low delay;it is fair and of low complexity;and it outperforms traditional iterative schedulers. We also propose two switch architectures suited for this scheduling scheme and analyze their hardware implementations. The arbiter circuit is simple, implementing only a FIFO queue. Only half as many arbiters for an iterative scheme are needed. The arbiters operate in complete parallel. They work for both architectures and make the hardware implementations sim-ple. The first architecture uses conventional queuing structure and crossbar. The second one uses separate memories for each queue at an input port and a special crossbar. This crossbar is simple and also has a re-duced diameter and distributed structure. We also show that the architectures have good scalability and re-quire almost no speedup.

低g值MEMS惯性开关研究进展

微机电系统(MEMS)惯性开关是集传感与执行为一体的无源电子器件,具有体积小、重量轻、易集成、加工一致性好、免装配等优势,在汽车工业、航空航天、武器装备等领域具有广阔的应用前景。低g值MEMS惯性开关的应用场景主要为飞行器加/减速过程特定功能的触发,在设计时应保证弹簧刚度低,质量块体积大,在结构设计与加工工艺中存在一定难度。本文介绍了低g值MEMS惯性开关的基本物理模型和工作原理,对国内外研究现状进行了阐述,总结了现阶段迫切需要解决的关键问题,并提出相应解决思路,为后续研究提供有益参考。

基于CIOQ架构改进iSLIP调度算法的研究

为了提高数据在传输过程中的性能指标和用户服务质量,针对CIOQ架构和iSLIP调度算法进行研究,提出了一种优先匹配队列信元数量达到满载的PMQF_iSLIP调度算法。算法先判断VOQ队列中的信元数量是否等于设置的最大容量,再根据判断结果执行不同的算法步骤,最终更新已完成匹配端口的优先级,在下一次匹配时,使端口具有优先匹配的权力。最后通过自己开发的数据交换仿真平台,对改进的算法进行仿真和分析,仿真结果表明,在相同的流量模型下,改进的算法减少了丢包率,增加了吞吐率。

一种公平服务的动态轮询调度算法

调度策略是核心路由交换设备性能的重要保证.针对联合输入交叉节点排队(combined input and cross-point queuing,简称CICQ)交换结构现有调度策略在复杂度或性能方面存在的缺陷,深入探讨了CICQ交换结构调度策略设计的基本准则,并提出了CICQ下虚拟通道的概念.基于基本准则和虚拟通道概念,提出一种简单、高效和公平服务的动态轮询调度策略——FDR(fair service and dynamic round robin).其算法复杂度为O(1),具有良好的可扩展性;并依据虚拟通道的状态为其分配调度份额,具有良好的动态实时性能,能够适应流量负载非均衡的网络环境.SPES(switching performance evaluation systcm)仿真结果表明,该算法具有良好的时延、吞吐量和抗突发性能.

排序集线器多级互连交换结构的多路径自路由模型

目前已提出多种能提供100%吞吐率的分组交换结构,如共享总线、共享内存、交叉矩阵及输入输出排队等.它们的结构性缺陷是存在某个瓶颈限制了其规模的有效扩展,如带宽瓶颈、调度算法运算处理瓶颈等.本研究提出了一类新的结合群组排序集线器和多级互连网络的多路径自路由交换结构,并证明了该类结构构建于代数群论的自路由数学模型.该结构具有:完全分布式自路由、无需端口匹配调度、无内部缓存、无缓存时延及无抖动、按位置换群建模及可递归扩展和模块化属性.理论分析及仿真结果表明该结构适合作为提供QoS保证的超大规模宽带交换结构.

RapidIO在多处理器系统互连中的应用

分析了传统的共享总线技术遇到的困难,介绍了新型总线技术RapidIO。结合实例,分析研究了RapidIO在多处理器系统互连中的应用。

新型的IBA刀片式集群服务器及其内部互联

从服务器分类以及应用的角度阐述了现有集群服务器的优劣势,指出以Infiniband为基础的刀片式集群服务器将更能适应服务的要求。最后,提出并分析了一种实现128个端口交换网的冗余互联结构。