Waveform digitization utilizing switched-capacitor arrays

Compared with traditional waveform digitization with flash-ADCs, waveform digitization with switched-capacitor arrays (SCAs) is able to achieve the sampling speed above 1 GS/s without degrading the analog to digital conversion precision significantly. In this paper, we present the implementation of a fast waveform digitization system with the use of SCAs, and evaluate its performance of waveform digitization and the waveform timing. At about 5 GS/s, the dynamic input range of the digitizer is about 66 dB, and its timing precision is about 20 ps (RMS).

Tunable Bandwidth Third Order Switched-Capacitor with Multiple Feedbacks Filter for Different Center Frequencies

This paper proposes third order tunable bandwidth active Switched-Capacitor filter. The circuit consists of only op-amps and switched capacitors. The circuit is designed for circuit merit factor Q = 10. The proposed circuit implements three filter functions low pass, band pass and high pass simultaneously in single circuit. The filter circuit can be used for both narrow as well as for wide bandwidth. For various values of cut-off frequencies the behaviour of circuit is studied. The circuit works properly only for higher central frequencies, when f0 > 10 kHz.

Design of Sixth-Order Lowpass Elliptic Switched-Capacitor Filter

In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower total harmonic distortion( THD) without deteriorating other performances. After system design in Simulink,the filter is realized in transistor level and finally fabricated in Central Semiconductor Manufacturing Corporation( CSMC) 0.5 μm metal-oxide-semiconductor( CMOS) technology. Typical measured results are: it operates with 25: 1 clock-to-corner frequency ratio and a 10 k Hz maximum corner frequency. The maximum passband ripple is about 0.49 d B and the minimum stopband rejection is 40 d B for the temperature from-20 ℃to 80 ℃. For the 250 k Hz clock frequency setting,given the 1 k Hz,- 8 d BVrms input signal,the measured worst case THD is-64 d B. The active area of the chip is 2.8 mm2 with 8 pads. The analog power dissipation is10 m W from a 5 V power supply.

NOVEL LINEAR TRANSFORMATION SWITCHED-CAPACITOR FILTER DESIGN

This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS filters.De-signed examples are given here.An Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic capacitances.The experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.

Multi-Phase QR ZCS Switched-Capacitor Bidirectional Power Converter for PV System Application

The multi-phase implementation in the QR （quasi resonant） ZCS （zero current switching） SC （switched capacitor） bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss and significantly increase the converter efficiency and power density. This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode. This is accomplished by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes. The size and cost can be reduced when the proposed converter has been designed with the coupled inductors. The simulation and experimental results have been used to demonstrate the performance of the two-phase with and without coupled inductor interleaved QR ZCS SC converters for bidirectional power flow control application, and an extending structure for N-phase is mentioned.

基于Switch-Capacitor网络实现分时供电的多输入升压变换器

在新能源联合发电系统中,多输入直流变换器可分时或同时向负载提供能量,具有简化系统结构、降低系统成本等优点。然而,现有的多输入直流变换器不能很好地满足新能源发电领域对高升压比、低纹波、低开关应力等技术参数的要求。因此,本文基于Switch-Capacitor网络串联放电、并联充电和多个网络累加升压的工作特性,推导出一种新型多输入升压变换器。本文以三输入升压变换器为例,详细分析了其在连续工作模式下的工作原理和工作性能,进行了仿真分析,并搭建了实验模型,仿真分析与实验研究的结果表明:①升压能力强,其升压比与Switch-Capacitor网络组中的网络个数有关;②开关器件的电压应力、输入电流纹波和输出电压纹波小;③所有开关管由同一控制信号隔离驱动,控制电路简单;④实现分时供电,元器件利用率高;⑤推演出对应的同时供电多输入升压变换器。

一种基于多谐振开关槽与Buck-Boost电路的准并联变换器

谐振开关电容变换器具有效率高、体积小、质量轻和易集成等优点,是中间母线变换器的理想拓扑,然而其不足之处在于电压比固定以及软开关特性易受谐振参数容差的影响。该文针对这两个问题,将多谐振开关槽式变换器与四开关Buck-Boost变换器进行结合,提出一种基于准并联架构的中间母线变换器,详细分析变换器的工作原理与电压增益特性。通过推导电流时域表达式详细分析谐振参数容差对变换器的影响,并给出参数设计的方法。该文研究一种合适的控制方式,完成环路补偿设计,实现输出电压的闭环控制。通过仿真和实验对上述理论和解决方案进行验证。

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors.The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers.The selective harmonic elimination(SHE)approach is used to remove the lower-order harmonics.The optimal switching angles for SHE is determined using the genetic algorithm.These switching angles are com-bined with a level-shifted pulse width modulation(PWM)technique for pulse generation,resulting in reduced total harmonic distortion(THD).A detailed com-parison has been made against other relevant seven-level inverter topologies in terms of the number of switches,drivers,diodes,capacitors,and boosting facil-ities to emphasize the benefits of the proposed model.The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results.The Digital Signal Processing(DSP)TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

基于Switched-RC技术的0.8V带通滤波器

开关电容滤波器是信号处理系统的重要组成模块，设计了一种用于心率检测设备的六阶带通开关电容滤波器。该设计基于开关电阻电容技术，利用开关电阻代替传统的采样开关，实现了更高的采样线性度，是低压下开关电容滤波器正常工作的一种全新实现方案。仿真结果表明，该滤波器在0.8V工作电压下，功耗为0.9mw，输出摆幅可达1.2Vp-p，通带增益为10dB，-3dB带宽为25-80Hz。

双开关二次型结构的耦合电感高增益DC-DC变换器

在能源危机和环境问题的背景下,高电压增益的DC-DC变换器成为利用可再生新能源不可或缺的环节。基于此,提出1种双开关二次型结构,使传统的二次型Boost变换器的电压增益得到有效提升,且降低了开关管的电流应力。结合开关电容和耦合电感,提出1种电压增益极高的双开关二次型结构耦合电感高增益DC-DC变换器。该变换器具有电压增益高、2个开关管同相、开关管和输出二极管电压应力低和多个二极管实现零电流关断的优点。详细分析了变换器的运行原理和稳态性能,包括电压增益推导、元器件电压电流应力等。制作了1款120 W样机,验证了理论分析的正确性和变换器的可行性。

Composite Converter Combined APFC with Switched-capacitor Converter

To reduce switch numbers and voltage stress in semiconductor devices,this paper proposes a novel single-phase converter combined Active Power Factor Correction(APFC)with switched-capacitor converter.In addition,dynamic voltage regulation and voltage gain are improved by integrating the boost converter and switching capacitor cells.The interstage bulk capacitor is no longer needed.An average current control with redistribution of voltage in cells is proposed to obtain voltage lift ability of the switching capacitor cells and maintain a high-power factor.To study and verify the proposed converter preliminarily,theoretical analysis and simulation are presented in the paper.Furthermore,a 50o W prototype with two different configurations is built for experimental verification.The proposed converter can reach 95.62%of maximum efficiency,0.99 of power factor,and 3.55%of THD with 600 V output voltage,simultaneously.

开关电容DC-DC转换器:从变压器模型到电路的演进

开关电容(Switched Capacitor,SC)DC-DC转换器在很多领域有着广泛的应用。为应对大电压转换比(Voltage Conversion Ratio,VCR)的情况,前人提出了诸多拓扑结构。常用的拓扑结构包括Dickson,Cockcroft-Walton,Series-Parallel,Ladder,Fibonacci,Divider等等。这些拓扑结构有着各自的性能特点,适用于不同的场景。然而,对于这些不同的拓扑结构是如何产生的,本质的区别是什么,各自的优缺点是什么,并无直观的解释和分析。因此,该文从开关电容DC-DC转换器的等效变压器模型入手,分析了各个拓扑之间的本质区别,并展示了从等效模型到实际电路的演进过程,解释了规则和原因。

Design of a Switched Capacitor Negative Feedback Circuit for a Very Low Level DC Current Amplifier

To miniaturize a very low level dc current amplifier and to improve its output response speed, the switched capacitor negative feedback circuit (SCNF), instead of the conventionally used high-ohmage resistor, is presented in this paper. In our system, a switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier using SCNF. The theoretical output voltage of the very low level dc current amplifier using SCNF is obtained. The experimental results show that the unnecessary components of the amplifier’s output are much decreased, and that the response speed of the amplifier with both the SCNF and SCF is faster than that using high-ohmage resistor.

改进型高增益耦合电感Boost-Sepic变换器

针对光伏电池输出电压等级低、稳定性差的问题,本文将Boost-Sepic变换器进行改进,并加入耦合电感与开关电容两种增益单元,提出一种高增益耦合电感组合Boost-Sepic变换器。首先将组合后的Boost-Sepic变换器中输入电感替换为耦合电感原边,保证输入侧电流连续并钳位开关管电压;同时将耦合电感倍压单元与开关电容进行串联以提高电压增益。采用无源钳位吸收回路回收耦合电感漏感的能量,抑制开关管两端产生的电压尖峰。详细分析了Boost-Sepic变换器的工作模态、电压增益、开关器件电压/电流应力及器件参数的选择,并与其他高增益变换器对比。最后,通过200 W实验样机验证了变换器的可行性与正确性。

Active Current Sharing of LCLC Resonant Converter with Switch-Controlled-Capacitor Technology

In this paper,an interleaved LCLC converter with enhancement-mode(E-mode)GaN devices is introduced to achieve the accurate current sharing performance for data center applications. Any tolerance in the resonant tank elements can lead to large load imbalance between any two different phases. Due to the steep gain curves of LCLC converters,conventional current sharing methods are not effective. In the proposed converter,the impedances of the resonant networks are matched by switching a capacitor,i.e.,switch controlled capacitor(SCC),in series with the resonant capacitor in one or some of the phases,which results in accurate load current sharing among the phases with an accuracy around 0.025%. The load share of a phase is sensed through the resonant current on it,and the control logic applied to such current sharing can be achieved. By this method,accurate current sharing is achieved for a wide input voltage range required for the hold-up time in data center applications. Interleaving is applied in the proposed multiphase LCLC converter,resulting in low current stress on the output capacitor and allowing ceramic capacitor implementation. Moreover,phase shedding accomplishes high light load efficiency. The performance of the proposed interleaved LCLC converter is verified by a two-phase 1 k W prototype with an input voltage ranging from 250 V to 400 V and a fixed 12 V output voltage.

Output Feedback Controller Design for Discrete-time Switched Singular Systems

This paper is concerned with the problems of robust admissibility and static output feedback( SOF)stabilization for a class of discrete-time switched singular systems with norm-bounded parametric uncertainties.The objective is to design a suitable robust SOF controller guaranteeing the regularity,causality and asymptotic stability of the resulting closed-loop system under arbitrary switching laws. Based on the basic matrix inequality sufficient condition for checking the admissibility of switched singular systems,together with some matrix inequality convexifying techniques,the SOF controller synthesis is developed for the underlying systems. It is shown that the controller gains can be obtained by solving a set of strict linear matrix inequalities( LMIs). A simulation example is given to show the effectiveness of the proposed method.

Switching of Capacitors in an Asymmetric Induction Motor with Single-Phase Power,Triggering Several Applied Loads

xThis study has as its objective to collaborate with the expansion in the market of electric energy in rural areas,offering as such an innovative prospect to the solution of associated problems through use of the asymmetric three-phase induction motor,supplied by a single-phase source.In this system,capacitor switching is applied during operation,while theoretical and practical results are presented for the application of this switching in a three-phase asymmetric induction motor of 20 hp.

Direct on Line Starting Induction Motor with Thyristor Switched Capacitor Based Voltage Regulation

The purpose of this paper is to show a laboratory scale implementation of a Thyristor Switched Capacitors （TSC） as an alternative for voltage regulation during a direct on line three-phase induction motor starting on an emulated weak transmission line. Thyristor switched capacitor bank was chosen because it is a well known topology, considering the very nature of the direct starting induction motors, which represents a highly inductive load, the use of switched reactors becomes unnecessary. Such fact minimizes the introduction of harmonics components, and also reduces the cost of the implementation. The binary disposition of the banks allows a variable Var compensation with sixteen steps, in this case. The solution makes use of low cost devices combined with sliding window voltage and current measurement algorithm and a PI control with dead band control for achieve the shown experimental results, where the system is able to manage a typically 20% voltage drop, reducing it to less than 4%. The schematic of the developed circuit, the control technique and a quite simple method to calculate the binary weight capacitors banks are also presented.

A High-Performance Operational Amplifier for High-Speed High-Accuracy Switch-Capacitor Cells

A high-speed high-accuracy fully differenttial operational amplifier （op-amp） is realized based on no-Miller-capacitor feedforward （NMCF） compensation scheme. In order to achieve a good phase margin, the NMCF compensation scheme uses the positive phase shift of left-half-plane （LHP） zero caused by the feedforvvard path to counteract the negative phase shift of the non-dominant pole. Compared to traditional Miller compensation method, the op-amp obtains high gain and wide band synchronously without the pole-splitting effect while saves significant chip area due to the absence of the Miller capacitor. Simulated by the 0.35 μm CMOS RF technology, the result shows that the open-loop gain of the op-amp is 118 dB with the unity gain-bandwidth （UGBW） of 1 GHz, and the phase margin is 61°while the settling time is 5.8 ns when achieving 0.01% accuracy. The op-amp is especially suitable for the front-end sample/hold （S/H） cell and the multiplying D/A converter （MDAC） module of the high-speed high-resolution pipelined A/D converters （AVCs）.