A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

Frequency Synthesizer of Short-Wave SFH/MFSK System

The technology of DDS-driven PLL is introduced and a new scheme of frequency synthesizer which is suitable for SW SFH/MFSK System is presented in this paper. Based on the special requirement of SW communication, a model of the scheme is given and the results show that the frequency synthesizer has small frequency insteval (≤0.1 Hz), short switch pierod (<200 ms) and high frequency stability as crystal oseillator.

BIT COMMITMENT USING PSEUDO-RANDOM SYNTHESIZER

This paper presents two practical message commitment schemes: one is suitable for committing many bits, and another is useful for committing any bit-long message. They are provably secure based on pseudo-random synthesizers. In these schemes, the sender may be unbounded to polynomial time and the receiver is bounded. The advantage of these schemes is that the secure parameter may be small.

Fast Switching Fractional-N Frequency Synthesizer Architecture Using TDTL

This paper presents an efficient indirect fractional frequency synthesizer architecture based on the time delay digital tanlock loop. The indirect type frequency synthesis systems incorporate a low complexity high performance adaptation mechanism that enables them to remain in a locked state following the division process. The performance of the proposed fractional-N synthesizer under various input conditions is demonstrated. This includes sudden changes in the system input frequency as well as the injection of noise. The results of the extensive set of tests indicate that the fractional-N synthesizer, proposed in this work, performs well and is capable of achieving frequency divisions with fine resolution. The indirect frequency synthesizer also has a wide locking range and fast switching response. This is reflected by the system ability to regain its lock in response to relatively large variations in the input frequency within a few samples. The overall system performance shows high resilience to noise as reflected by the mean square error results.

TDTL Based Frequency Synthesizers with Auto Sensing Technique

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

A fractional-N frequency synthesizer for wireless sensor network nodes

This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontrolled oscillator（VCO） with small VCO gain（KVCO） and frequency step（fstep） variations, a charge pump（CP）with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups＇ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86：34 dBc/Hz at 100 k Hz offset and 114：17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes＇ requirements.

Optical frequency synthesizer with an integrated erbium tunable laser

Optical frequency synthesizers have widespread applications in optical spectroscopy,frequency metrology,and many other fields.However,their applicability is currently limited by size,cost,and power consumption.Silicon photonics technology,which is compatible with complementary-metal-oxide-semiconductor fabrication processes,provides a low-cost,compact size,lightweight,and low-power-consumption solution.In this work,we demonstrate an optical frequency synthesizer using a fully integrated silicon-based tunable laser.The synthesizer can be self-calibrated by tuning the repetition rate of the internal mode-locked laser.A 20 nm tuning range from 1544 to 1564 nm is achieved with~10−13 frequency instability at 10 s averaging time.Its flexibility and fast reconfigurability are also demonstrated by fine tuning the synthesizer and generating arbitrary specified patterns over time-frequency coordinates.This work promotes the frequency stability of silicon-based integrated tunable lasers and paves the way toward chip-scale lowcost optical frequency synthesizers.

A class-CVCO based Σ–Δ fraction-N frequency synthesizer with AFC for 802.11ah applications

A 1.4-2 GHz phase-locked loop （PLL） ∑-△ fraction-N frequency synthesizer with automatic fre- quency control （AFC） for 802.1 lah applications is presented. A class-C voltage control oscillator （VCO） ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order ∑-△ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of 〈 -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.

A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

A 40-GHz phase-locked loop（PLL） frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator（VCO） to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector（PFD）and the charge pump（CP） are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.

Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.

A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13μm CMOS technology.The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter.A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration.Pulse-swallow topology with a multistage noise shaping△Σmodulator is adopted in the frequency divider design.The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes.Measurement results show that the phase noise of the synthesizer achieves -91.3 dBc/Hz and -117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset,separately.The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm;.

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3μs.

A low phase noise and low spur PLL frequency synthesizer for GNSS receivers

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.

A wideband frequency synthesizer for a receiver application at multiple frequencies

An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18μm 1P6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator （VCO） based on a reconfigurable LC tank with a binaryweighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are -122.13 dBc/Hz, -122.19 dBc/Hz, -121.8 dBc/Hz and -121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are -80.09 dBc/Hz, -80.29 dBc/Hz, -83.05 dBc/Hz and -86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 mW from a 2 V power supply. The chip size is 1.5 × 1 mm2.

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS

This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.

A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time.It incorporates two phase-locked loops and one single-sideband （SSB） mixer.A 2-to-1 multiplexer with high linearity is proposed.A modified wideband SSB mixer,quadrature VCO, and layout techniques are also employed.The synthesizer is fabricated in a 0.18μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current.The measured phase noise is -128 dBc/Hz at 10 MHz offset,and the sideband rejection is -22 dBc at 7.656 GHz.

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

A low-spurious fast-hopping MB-OFDM UWB synthesizer

A frequency synthesizer for the ultra-wide band（UWB） group #1 is proposed.The synthesizer uses a phaselocked loop（PLL） and single-sideband（SSB） mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with±264 MHz and 792 MHz,respectively.A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high linearity.The synthesizer is fabricated in Jazz 0.18-μm RF CMOS technology.The measured reference spur is as low as-69 dBc and the maximum spur is the LO leakage of-32 dBc.A low phase noise of—110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86°are achieved.The hopping time between different bands is less than 1.8 ns.The synthesizer consumes 30 mA from a 1.8V supply.

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.