In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a...In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.展开更多
基金supported by the National Key Research and Development Program of China(2021YFB2011700).
文摘In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
文摘对自主研发的多羟多胺络合剂(FA/O)在硅通孔技术(Through-silicon-via,TSV)化学机械平坦化(chemical mechanical planarization,CMP)进行了应用研究。结果表明,FA/O络合剂较其它常用络合剂在碱性CMP条件下对铜有较高的去除速率,抛光液中不加FA/O络合剂时,铜的去除速率仅为45.0nm/min,少量FA/O的加入迅速提高了铜膜去除速率,当FA/O含量为50mL/L时,铜去除速率趋于平缓。在TSV Cu CMP中应用表明,FA/O对铜的去除率可高达2.8μm/min,满足微电子技术进一步发展的要求。
