Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coati...Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of-6 μm and depth of-54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treat- ment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm2, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm2 under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even un- der test temperature as high as 125℃. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO2 interlayer dielectric （ILD） fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.展开更多
A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency r...A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.展开更多
Vacuum-assisted spin-coating is an effective polymer filling technology for sidewall insulating of through-silicon-via(TSV).This paper investigated the flow mechanism of the vacuum-assisted polymer filling process bas...Vacuum-assisted spin-coating is an effective polymer filling technology for sidewall insulating of through-silicon-via(TSV).This paper investigated the flow mechanism of the vacuum-assisted polymer filling process based on experiments and numerical simulation,and studied the effect of vacuum pressure,viscosity of polymer and aspect-ratio of trench on the filling performance.A 2D axisymmetric model,consisting of polymer partially filled into the trench and void at the bottom of trench,was developed for the computational fluid dynamics(CFD)simulation.The simulation results indicate that the vacuum-assisted polymer filling process goes through four stages,including bubble formation,bubble burst,air elimination and polymer re-filling.Moreover,the simulation results suggest that the pressure significantly affects the bubble formation and the polymer re-filling procedure,and the polymer viscosity and the trench aspect-ratio influence the duration of air elimination.展开更多
This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via（TSV） in three-dimensional（3 D） integrated circuits. The proposed analytical model is vali...This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via（TSV） in three-dimensional（3 D） integrated circuits. The proposed analytical model is validated by the commercial FEM tool—COMSOL. The comparison between the results of the proposed analytical formulas and COMSOL shows that the proposed formulas have very high accuracy with a maximum error of 0.1%.Based on the analytical model, the temperature performance of TSV is studied. Design guide lines of TSV are also given as：（1） the radius of the TSV increases, the resistance decreases and the temperature can be increased;（2） the thicker the dielectric layer, the higher the temperature;（3） compared with carbon nanotube, the Cu enlarges the temperature by 34 K, and the W case enlarges the temperature by 41 K.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.61404008&61574016)"111"Project of China(Grant No.B14010)
文摘Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of-6 μm and depth of-54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treat- ment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm2, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm2 under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even un- der test temperature as high as 125℃. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO2 interlayer dielectric （ILD） fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.
基金Project supported by the National Natural Science Foundation of China(No.61234001)the Shanghai Science and Technology Committee(No.13511500900)the Specialized Research Fund for the Doctoral Program of Higher Education(No.20120073130003)
文摘A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.
文摘Vacuum-assisted spin-coating is an effective polymer filling technology for sidewall insulating of through-silicon-via(TSV).This paper investigated the flow mechanism of the vacuum-assisted polymer filling process based on experiments and numerical simulation,and studied the effect of vacuum pressure,viscosity of polymer and aspect-ratio of trench on the filling performance.A 2D axisymmetric model,consisting of polymer partially filled into the trench and void at the bottom of trench,was developed for the computational fluid dynamics(CFD)simulation.The simulation results indicate that the vacuum-assisted polymer filling process goes through four stages,including bubble formation,bubble burst,air elimination and polymer re-filling.Moreover,the simulation results suggest that the pressure significantly affects the bubble formation and the polymer re-filling procedure,and the polymer viscosity and the trench aspect-ratio influence the duration of air elimination.
基金supported by the National Natural Science Foundation of China(Nos.61574106,61574104)the National Defense Pre-Research Foundation of China(No.9140A23060115DZ01062)the Key Science and Technology Special Project of Shaanxi Province(No.2015KTCQ01-5)
文摘This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via（TSV） in three-dimensional（3 D） integrated circuits. The proposed analytical model is validated by the commercial FEM tool—COMSOL. The comparison between the results of the proposed analytical formulas and COMSOL shows that the proposed formulas have very high accuracy with a maximum error of 0.1%.Based on the analytical model, the temperature performance of TSV is studied. Design guide lines of TSV are also given as：（1） the radius of the TSV increases, the resistance decreases and the temperature can be increased;（2） the thicker the dielectric layer, the higher the temperature;（3） compared with carbon nanotube, the Cu enlarges the temperature by 34 K, and the W case enlarges the temperature by 41 K.
