A Test Pattern Identification Algorithm and Its Application to CINRAD/SA(B) Data

A variety of faulty radar echoes may cause serious problems with radar data applications,especially radar data assimilation and quantitative precipitation estimates.In this study,＂test pattern＂ caused by test signal or radar hardware failures in CINRAD （China New Generation Weather Radar） SA and SB radar operational observations are investigated.In order to distinguish the test pattern from other types of radar echoes,such as precipitation,clear air and other non-meteorological echoes,five feature parameters including the effective reflectivity data percentage （Rz）,velocity RF （range folding） data percentage （RRF）,missing velocity data percentage （RM）,averaged along-azimuth reflectivity fluctuation （RNr,z） and averaged along-beam reflectivity fluctuation （RNa,z） are proposed.Based on the fuzzy logic method,a test pattern identification algorithm is developed,and the statistical results from all the different kinds of radar echoes indicate the performance of the algorithm.Analysis of two typical cases with heavy precipitation echoes located inside the test pattern are performed.The statistical results show that the test pattern identification algorithm performs well,since the test pattern is recognized in most cases.Besides,the algorithm can effectively remove the test pattern signal and retain strong precipitation echoes in heavy rainfall events.

Enhancing SAT-Based Test Pattern Generation

This paper presents modeling tools based on Boolean satisfiability (SAT) to solve problems of test generation for combinational circuits. It exploits an added layer to maintain circuit-related information and value justification relations to a generic SAT algorithm. It dovetails binary decision graphs (BDD) and SAT techniques to improve the efficiency of automatic test pattern generation (ATPG). More specifically, it first exploits inexpensive reconvergent fanout analysis of circuit to gather information on the local signal correlation by using BDD learning, then uses the above learned information to restrict and focus the overall search space of SAT-based ATPG. Its learning technique is effective and lightweight. The experimental results demonstrate the effectiveness of the approach.

Dependence of single event upsets sensitivity of low energy proton on test factors in 65 nm SRAM

In order to accurately predict the single event upsets （SEU） rate of on-orbit proton, the influence of the proton energy distribution, incident angle, supply voltage, and test pattern on the height, width, and position of SEU peak of low energy protons （LEP） in 65 nm static random access memory （SRAM） are quantitatively evaluated and analyzed based on LEP testing data and Monte Carlo simulation. The results show that different initial proton energies used to degrade the beam energy will bring about the difference in the energy distribution of average proton energy at the surface and sensitive region of the device under test （DUT）, which further leads to significant differences including the height of SEU peak and the threshold energy of SEU. Using the lowest initial proton energy is extremely important for SEU testing with low energy protons. The proton energy corresponding to the SEU peak shifts to higher average proton energies with the increase of the tilt angle, and the SEU peaks also increase significantly. The reduction of supply voltage lowers the critical charge of SEU, leading to the increase of LEP SEU cross section. For standard 6-transitor SRAM with bit-interleaving technology, SEU peak does not show clear dependence on three test patterns of logical checkerboard 55H, all＂ 1＂, and all ＂0＂. It should be noted that all the SEUs in 65 nm SRAM are single cell upset in LEP testing due to proton＇s low linear energy transfer （LET） value.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

SACSR:a low power BIST method for sequential circuits

A novel built-in-self-test(BIST) method called seeded autonomous cyclic shift register (SACSR) is presented to reduce test power of the sequential circuit. The key idea is to use a pseudorandom pattern generator and several XOR gates to generate seeds that share fewer test vectors. The generated seed is taken XOR operation with a cyclic shift register, and the single input change (SIC) sequence is generated. The proposed scheme is easily implemented and can reduce the switching activities of the circuit under test (CUT) greatly. Experimental results on ISCAS89 benchmarks show that on average more than 63% power reduction can be achieved. It also demonstrates that the generated test vectors attain high fault coverage for stuck-at fault and transition fault coverage with short test length.

A virtual logic analyzer implemented with Arduino

A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.

The structure-based multi-fault test generation algorithm for combinational circuit

In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.

Comparative Study on Physical Fitness Test Models of Chinese, Japanese and American Students

The physical health of adolescents is related to the future of the nation and the competitiveness of the country.Through a comparative analysis of the backgrounds,organizations,testing programs and evolution processes of physical health tests in China,Japan and the United States,the three countries are explored.The development trends and problems of student physical fitness tests,find the differences,learn about the research results and experiences of physical fitness tests in Japan and the United States,draw on Japanese and American management models and successful cases,and propose some methods to optimize and improve China's physical fitness test models.It is recommended to make full use of the existing resources to promote the improvement of students'physical fitness.

Efficient Static Compaction of Test Patterns Using Partial Maximum Satisfiability

Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.

HTDet:A Clustering Method Using Information Entropy for Hardware Trojan Detection

Hardware Trojans(HTs)have drawn increasing attention in both academia and industry because of their significant potential threat.In this paper,we propose HTDet,a novel HT detection method using information entropybased clustering.To maintain high concealment,HTs are usually inserted in the regions with low controllability and low observability,which will result in that Trojan logics have extremely low transitions during the simulation.This implies that the regions with the low transitions will provide much more abundant and more important information for HT detection.The HTDet applies information theory technology and a density-based clustering algorithm called Density-Based Spatial Clustering of Applications with Noise(DBSCAN)to detect all suspicious Trojan logics in the circuit under detection.The DBSCAN is an unsupervised learning algorithm,that can improve the applicability of HTDet.In addition,we develop a heuristic test pattern generation method using mutual information to increase the transitions of suspicious Trojan logics.Experiments on circuit benchmarks demonstrate the effectiveness of HTDet.

Simulation of ATPG Neural Network and Its Experimental Results

This paper first establishes a neural network model for logic circuits fromthe truth table by using linear equations theory, presents a kind of ATPG neuralnetwork model, and investigates energy local minima for the network- And then,it proposes the corresponding techniques to reduce the number of energy localminima as well as some approaches to escaping from local minimum of eliergyFinally, two simulation systems, the binary ATPG neural network and thecontinuous ATPG neural network, are implemented oli SUN 3/260 workstationin C language. The experimental results and their analysis and discussion aregiven. The preliminary experimental results show that this method is feasibleand promising.