±800-kV UHVDC demonstration project passed live line test

On December 26, 2009, in the main control room of Shanghai Fengxian Converter Station, the voltage value on the screen rose from zero to 800 kV. This represented the demonstrative ±800-kV

Design of 1000-kV AC Single-Circuit Overhead Transmission Line

The UHVAC 1 000-kV transmission system is so far the one with the most advanced transmission technique applied and highest operation voltage.There are no guidelines or standards available for the design of 1 000-kV overhead transmission line in China.Study on key technologies and design schemes shall be carried out to ascertain the technical principles and construction standards for project construction,which are presented in this paper based on the Southeast Shanxi-Nanyang-Jingmen test and demonstration transmission line.A comparison and analysis of technical data and economic indices between UHV line and other lines are also described.

New Test Light Spectrum Design for L/U-Band Extended Optical Fiber Line Testing System

This paper describes a new design for the test light source of an L/U-band extended optical fiber line testing system and the side-band suppresser ratio of the test light should be more than 70 dB.

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.