Implementation of sub-100 nm vertical channel-all-around(CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In-Ga-Zn-O(IGZO) channel based thin-film transistors(TFT), which exhibit high on-off current ratio and relatively high mobility, has been widely researched due to its back end of line(BEOL)-compatible potential for the next generation dynamic random access memory(DRAM) application. In this work, thermal atomic layer deposition(TALD) indium gallium zinc oxide(IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition(ALD) process. In addition, thin-film transistors(TFTs) with vertical channel-all-around(CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Numerical Study and Optimization of CZTS-Based Thin-Film Solar Cell Structure with Different Novel Buffer-Layer Materials Using SCAPS-1D Software

This study explored the performances of CZTS-based thin-film solar cell with three novel buffer layer materials ZnS, CdS, and CdZnS, as well as with variation in thickness of buffer and absorber-layer, doping concentrations of absorber-layer material and operating temperature. Our aims focused to identify the most optimal thin-film solar cell structure that offers high efficiency and lower toxicity which are desirable for sustainable and eco-friendly energy sources globally. SCAPS-1D, widely used software for modeling and simulating solar cells, has been used and solar cell fundamental performance parameters such as open-circuited voltage (), short-circuited current density (), fill-factor() and efficiency() have been optimized in this study. Based on our simulation results, it was found that CZTS solar cell with Cd0.4Zn0.6S as buffer-layer offers the most optimal combination of high efficiency and lower toxicity in comparison to other structure investigated in our study. Although the efficiency of Cd0.4Zn0.6S, ZnS and CdS are comparable, Cd0.4Zn0.6S is preferable to use as buffer-layer for its non-toxic property. In addition, evaluation of performance as a function of buffer-layer thickness for Cd0.4Zn0.6S, ZnS and CdS showed that optimum buffer-layer thickness for Cd0.4Zn0.6S was in the range from 50 to 150nm while ZnS offered only 50 – 75 nm. Furthermore, the temperature dependence performance parameters evaluation revealed that it is better to operate solar cell at temperature 290K for stable operation with optimum performances. This study would provide valuable insights into design and optimization of nanotechnology-based solar energy technology for minimizing global energy crisis and developing eco-friendly energy sources sustainable and simultaneously.

Numerical Analysis on the Effect of n-Si on Cu(In, Ga)Se2 Based Thin-Films for High-Performance Solar Cells by 1D-SCAPS

We report the performances of a chalcopyrite Cu(In, Ga)Se2 CIGS-based thin-film solar cell with a newly employed high conductive n-Si layer. The data analysis was performed with the help of the 1D-Solar Cell Capacitance Simulator (1D-SCAPS) software program. The new device structure is based on the CIGS layer as the absorber layer, n-Si as the high conductive layer, i-In2S3, and i-ZnO as the buffer and window layers, respectively. The optimum CIGS bandgap was determined first and used to simulate and analyze the cell performance throughout the experiment. This analysis revealed that the absorber layer’s optimum bandgap value has to be 1.4 eV to achieve maximum efficiency of 22.57%. Subsequently, output solar cell parameters were analyzed as a function of CIGS layer thickness, defect density, and the operating temperature with an optimized n-Si layer. The newly modeled device has a p-CIGS/n-Si/In2S3/Al-ZnO structure. The main objective was to improve the overall cell performance while optimizing the thickness of absorber layers, defect density, bandgap, and operating temperature with the newly employed optimized n-Si layer. The increase of absorber layer thickness from 0.2 - 2 µm showed an upward trend in the cell’s performance, while the increase of defect density and operating temperature showed a downward trend in solar cell performance. This study illustrates that the proposed cell structure shows higher cell performances and can be fabricated on the lab-scale and industrial levels.

All-Solid-State Thin-Film Lithium-Sulfur Batteries

Lithium-sulfur(Li-S)system coupled with thin-film solid electrolyte as a novel high-energy micro-battery has enormous potential for complementing embedded energy harvesters to enable the autonomy of the Internet of Things microdevice.However,the volatility in high vacuum and intrinsic sluggish kinetics of S hinder researchers from empirically integrating it into allsolid-state thin-film batteries,leading to inexperience in fabricating all-solid-state thin-film Li-S batteries(TFLSBs).Herein,for the first time,TFLSBs have been successfully constructed by stacking vertical graphene nanosheets-Li2S(VGsLi2S)composite thin-film cathode,lithium-phosphorous-oxynitride(LiPON)thin-film solid electrolyte,and Li metal anode.Fundamentally eliminating Lipolysulfide shuttle effect and maintaining a stable VGs-Li2S/LiPON interface upon prolonged cycles have been well identified by employing the solid-state Li-S system with an“unlimited Li”reservoir,which exhibits excellent longterm cycling stability with a capacity retention of 81%for 3,000 cycles,and an exceptional high temperature tolerance up to 60℃.More impressively,VGs-Li2S-based TFLSBs with evaporated-Li thin-film anode also demonstrate outstanding cycling performance over 500 cycles with a high Coulombic efficiency of 99.71%.Collectively,this study presents a new development strategy for secure and high-performance rechargeable all-solid-state thin-film batteries.

Stability of high-salinity-enhanced foam:Surface behavior and thin-film drainage

Cocamidopropyl hydroxyl sulfobetaine(CHSB)is one of the most promising foaming agents for high-salinity reservoirs because the salt in place facilitates its foam stability,even with salinity as high as 2×10^(5)mg/L.However,the synergistic effects between CHSB and salt have not been fully understood.This study utilized bulk foam tests and thin-film interferometry to comprehensively investigate the macroscopic and microscopic decay processes of CHSB foams with NaCl concentrations ranging from 2.3×10^(4)to 2.1×10^(5)mg/L.We focused on the dilatational viscoelasticity and dynamic thin-film thickness to elucidate the high-salinity-enhanced foam stability.The increase in dilatational viscoelasticity and supramolecular oscillating structural force(Π_(OS))with salinity dominated the superior stability of CHSB foam.With increasing salinity,more CHSB molecules accumulated on the surface with a lower diffusion rate,leading to high dilatational moduli and surface elasticity,thus decelerating coarsening and coalescence.Meanwhile,the number density of micelles in the thin film increased with salinity,resulting in increasedΠOS.Consequently,the energy barrier for stepwise thinning intensified,and the thin-film drainage slowed.This work conduces to understand the mechanisms behind the pronounced stability of betaine foam and can promote the widespread application of foam in harsh reservoirs.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

Enhanced efficiency of the Sb_(2)Se_(3)thin-film solar cell by the anode passivation using an organic small molecular of TCTA

Antimony selenide(Sb_(2)Se_(3))is an emerging solar cell material.Here,we demonstrate that an organic small molecule of 4,4',4''-tris(carbazol-9-yl)-triphenylamine(TCTA)can efficiently passivate the anode interface of the Sb_(2)Se_(3)solar cell.We fabricated the device by the vacuum thermal evaporation,and took ITO/TCTA(3.0 nm)/Sb_(2)Se_(3)(50 nm)/C60(5.0 nm)/Alq3(3.0 nm)/Al as the device architecture,where Alq3 is the tris(8-hydroxyquinolinato)aluminum.By introducing a TCTA layer,the open-circuit voltage is raised from 0.36 to 0.42 V,and the power conversion efficiency is significantly improved from 3.2%to 4.3%.The TCTA layer not only inhibits the chemical reaction between the ITO and Sb_(2)Se_(3)during the annealing process but it also blocks the electron diffusion from Sb_(2)Se_(3)to ITO anode.The enhanced performance is mainly attributed to the suppression of the charge recombination at the anode interface.

High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

Advances in mobility enhancement of ITZO thin-film transistors:a review

Indium-tin-zinc oxide(ITZO)thin-film transistor(TFT)technology holds promise for achieving high mobility and offers significant opportunities for commercialization.This paper provides a review of progress made in improving the mobility of ITZO TFTs.This paper begins by describing the development and current status of metal-oxide TFTs,and then goes on to explain the advantages of selecting ITZO as the TFT channel layer.The evaluation criteria for TFTs are subsequently introduced,and the reasons and significance of enhancing mobility are clarified.This paper then explores the development of high-mobility ITZO TFTs from five perspectives:active layer optimization,gate dielectric optimization,electrode optimization,interface optimization,and device structure optimization.Finally,a summary and outlook of the research field are presented.

一种基于耦合电感的高增益软开关谐振变换器

该文提出了一种具有高增益、软开关的新型谐振变换器。该谐振变换器使用耦合电感来提高电压增益,升压比不仅取决于占空比,还取决于耦合电感的变比,具有高增益的优点。此外,由于采用了有源钳位技术,漏感中的能量可以被回收利用,用来对开关管的结电容充放电提供能量,从而实现软开关。由于采用了耦合电感,所提出的变换器可以在较低的开关管电压应力的情况下实现较高的输出电压,因此可以使用低导通电阻的低压器件,从而提升系统的效率。该文分析了该谐振变换器的工作原理,并推导了输出电压、关断电流应力等参数的解析表达式。在此基础上,从理论上分析了该变换器取得软开关的条件,并对该变换器的各个器件的电压电流应力进行分析,为器件选型提供了理论依据。最后,搭建1kW实验样机,针对该文提出的基于耦合电感的谐振变换器的高增益、软开关、低电压应力、高效率等性能进行了实验验证。通过实验得出所提出的拓扑可以在10倍增益的情况下达到最高97.5%的效率,表明所提拓扑的优越性。

一种应用于两相交错Boost的耦合电感的优化设计

两相交错Boost变换器具有纹波电流小的优势,但其采用的交错并联技术增加了电感数量,进而增加了装置的体积和重量,不利于其功率密度的提升。耦合电感通过将多个磁性元件集成到一个磁芯实现磁路的部分共享,从而减小了磁元件的数量和重量。因此,设计了一种反向耦合电感,并将其应用于两相交错Boost变换器,实现了装置功率密度的提升。首先,对反向耦合电感的工作原理和损耗来源进行分析;然后,在此基础上设计了一种改进的“EE”型磁芯,一方面有效提高了磁芯利用率,另一方面降低了电感的体积与重量;最后,通过有限元仿真对所提优化设计方案进行验证,同时搭建了功率等级为2 kW的两相交错Boost变换器实验平台。仿真和实验结果均验证了所提优化设计方案的有效性。

基于二次型升压变换器和开关电容的混合式升压方案研究

提出一种混合式高升压比DC-DC变换器。该变换器由二次型升压变换器、开关电容和耦合电感单元集成。为了减少元件的数量,耦合电感一次侧与二次型升压变换器共用;二次型升压变换器的输出电容一分为二,并与开关电容共用。由于电源和负载之间的共地特性,则输入电流连续。对所提变换器的电压增益进行了推导,并分析其电压应力。结果表明所提逆变器具备高电压增益、低电压应力的特性。最后,搭建了80 W的实验样机,实验结果验证了所提变换器的正确性和有效性。

一种应用于光伏的高增益DC/DC变换器研究

基于耦合电感、开关电容与输入电压源组成的基本功率单元,提出一种集成式新型DC/DC变换器。该拓扑结构具有模块化和可扩展性,耦合电感和开关电容结构组成的倍压单元提升了电路的升压比。漏感能量通过钳位电路回收,以降低开关管电压应力和功率损耗;同时缓解了二极管的反向恢复问题,优化了开关管和二极管的选择。详细介绍了稳态分析、工作原理和设计考虑;最后并制作了90 W实验样机,验证了理论分析的正确性。

基于寄生电感优化的分立器件布局方法研究

为了探究分立器件与PCB组合形成的半桥电路时采用何种布局方式才能尽最大限度减小线路寄生电感的问题,基于换流回路寄生电感概念,提出了一种经优化的分立器件在PCB上的布局方式,进而减小换流回路的寄生电感,随后通过有限元仿真软件评估并验证不同布局方式所产生的寄生电感,并结合LTspice电路仿真软件评估不同布局方式对器件电开关特性的影响,最后通过双脉冲实验验证了所设计的一种经过优化布局半桥电路的优越性.所提供的半桥电路的设计方法为分立器件在PCB上的布局提供了理论和技术支撑.

一种交叉倍压型高增益DC/DC变换器

针对光伏发电、燃料电池发电等领域对高增益直流变换器的需求,以两相交错并联升压变换器为研究对象,由2个含有电感的倍压单元组合设计出实现电压提升的交叉倍压结构,据此提出了一种新颖的交叉倍压型高增益DC/DC变换器。该变换器可实现(3n+4)/(1-d)倍的高电压增益(1∶n为耦合电感匝数比,d为变换器占空比),且具有电路器件的低电压应力特性。对于漏感引起的开关管电压尖峰问题,引入了钳位电容构成释放漏感能量通道,同时提升了输出电压。介绍了新型交叉倍压型高增益变换器的拓扑结构,分析了变换器各模态的工作过程,推导了电压增益、输入电流纹波及各器件电压应力等稳态特性,并搭建样机进行实验研究,验证了该直流变换技术方案的可行性和先进性。

高增益耦合电感组合Boost-Cuk变换器

为了解决传统变换器电压增益低的问题,将Boost变换器与Cuk变换器进行并联集成,并利用耦合电感倍压技术提高变换器的电压增益。设计而成的高增益耦合电感组合Boost-Cuk变换器保留了Cuk变换器输出电流的连续性,新型结构中使用无源钳位来吸收漏感能量,对寄生电容与漏感谐振引起的电压尖峰起到约束作用,降低了开关管的电压应力。描述了变换器电感电流连续模式(Continuous current mode,CCM)下的运行特点,并进行了该变换器的参数设计。最后,通过搭建一台100 W的试验样机来求证理论的正确性。

新型高增益耦合电感二次型变换器

将开关-耦合电感单元引入二次型变换器,采用一个耦合电感和两个独立电感,在开关管关断时,电感为电容充电;导通时,利用电容为负载供电。与传统变换器相比,所提出的变换器采用更少的器件,能得到高电压增益效果与低占空比。采用了降低电压应力的电容,二极管和半导体开关,开关管应力更低。提出了稳态和比较性能分析,制作了一台140W实验平台,给出实验数据与结论,验证了理论分析的正确性。

基于开关电感的宽电压增益双向DC/DC变换器

此处提出了一种用于储能系统的基于开关电感的宽电压增益双向DC/DC变换器。该变换器在实现双向升降压的同时进一步扩大了双向变换器的电压增益,可以适应不同电压等级的储能电池;相同电压增益下功率器件占空比有效降低,进一步减小了输入电流纹波,有助于提高电池充电性能。分析了放电和充电两种工作模式的工作原理,并搭建实验样机进行验证。实验结果表明在输出电压稳定的工况下,该变换器放电模式可以实现0.5~5倍的电压增益,充电模式可以实现0.2~2倍的电压增益,证明了所提变换器的双向升降压能力和宽电压增益能力。

卧式反应釜电磁感应加热设计

针对大型反应釜的感应加热难以进行大量实验验证的问题,通过将理论计算与有限元仿真相结合的方式,对计算得出的参数进行优化,选择合适的输出功率和谐振频率,完成感应器的设计。通过仿真可以更好对比不同匝数、自热对流和搅拌轴对加热的影响,更直观地查看工件温度分布情况,缩小计算参数误差,实现反应釜加热的工艺要求。