Heterojunction-engineered carrier transport in elevated-metal metal-oxide thin-film transistors

This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.

Implementation of sub-100 nm vertical channel-all-around(CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In-Ga-Zn-O(IGZO) channel based thin-film transistors(TFT), which exhibit high on-off current ratio and relatively high mobility, has been widely researched due to its back end of line(BEOL)-compatible potential for the next generation dynamic random access memory(DRAM) application. In this work, thermal atomic layer deposition(TALD) indium gallium zinc oxide(IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition(ALD) process. In addition, thin-film transistors(TFTs) with vertical channel-all-around(CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

Advances in mobility enhancement of ITZO thin-film transistors:a review

Indium-tin-zinc oxide(ITZO)thin-film transistor(TFT)technology holds promise for achieving high mobility and offers significant opportunities for commercialization.This paper provides a review of progress made in improving the mobility of ITZO TFTs.This paper begins by describing the development and current status of metal-oxide TFTs,and then goes on to explain the advantages of selecting ITZO as the TFT channel layer.The evaluation criteria for TFTs are subsequently introduced,and the reasons and significance of enhancing mobility are clarified.This paper then explores the development of high-mobility ITZO TFTs from five perspectives:active layer optimization,gate dielectric optimization,electrode optimization,interface optimization,and device structure optimization.Finally,a summary and outlook of the research field are presented.

Indium-gallium-zinc-oxide thin-film transistors:Materials,devices,and applications

Since the invention of amorphous indium-gallium-zinc-oxide(IGZO)based thin-film transistors(TFTs)by Hideo Hosono in 2004,investigations on the topic of IGZO TFTs have been rapidly expanded thanks to their high electrical performance,large-area uniformity,and low processing temperature.This article reviews the recent progress and major trends in the field of IGZO-based TFTs.After a brief introduction of the history of IGZO and the main advantages of IGZO-based TFTs,an overview of IGZO materials and IGZO-based TFTs is given.In this part,IGZO material electron travelling orbitals and deposition methods are introduced,and the specific device structures and electrical performance are also presented.Afterwards,the recent advances of IGZO-based TFT applications are summarized,including flat panel display drivers,novel sensors,and emerging neuromorphic systems.In particular,the realization of flexible electronic systems is discussed.The last part of this review consists of the conclusions and gives an outlook over the field with a prediction for the future.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.

Modeling of an Internal Stress and Strain Distribution of an Inverted Staggered Thin-Film Transistor Based on Two-Dimensional Mass-Spring-Damper Structure

Equipped with a two-dimensional topological structure,a group of masses,springs and dampers can be demonstrated to model the internal dynamics of a thin-film transistor(TFT).In this paper,the two-dimensional Mass-Spring-Damper(MSD)representation of an inverted staggered TFT is proposed to explore the TFT’s internal stress/strain distributions,and the stress-induced effects on TFT’s electrical characteristics.The 2DMSD model is composed of a finite but massive number of interconnected cellular units.The parameters,such as mass,stiffness,and damping ratios,of each cellular unit are approximated from constitutive equations of the compositematerials,while the electrical properties of the inverted staggered TFT are characterized by utilizing an electro-mechanical coupling relation derived from the quantum mechanics.TFTs are often used in biomedical sensors/transducers attached to human skins,and,for the purpose of simulation and validation,the boundary conditions on the interface between the TFT and the human skin were modeled as a spatially distributed sinusoidal excitation with a frequency of 50 Hz,assuming the TFT thickness is more than tens of microns.The fidelity of the 2D MSD structure in the modeling of an inverted staggered TFT is verified by comparing its simulated total displacement fieldwith that of a finite element analysis(FEA)model.The advantages of the MSD model include a dramatic reduction in memory use by up to 60%and faster computation times that are up to 80%lower.More importantly,the MSD model is better suited than FEA to many problems in accurate tissue modeling for medical applications,for which FEA is becoming a bottleneck.This work develops a novel modeling approach,which can be extended to other types of flexible thin film transistors.

Al_(2)O_(3)/HfO_(2) Nanolaminate Dielectric Boosting IGZO-Based Flexible Thin-Film Transistors

Flexible thin-film transistors(TFTs)have attracted wide interest in the development of flexible and wearable displays or sensors.However,the conventional high processing temperatures hinder the preparation of stable and reliable dielectric materials on flexible substrates.Here,we develop a stable laminated Al_(2)O_(3)/HfO_(2) insulator by atomic layer deposition at a relatively lower temperature of 150℃.A sputtered amorphous indium-gallium-zinc oxide(IGZO)with the stoichiometry of In_(0.37)Ga_(0.20)Zn_(0.18)O_(0.25) is used as the active channel material.The flexible TFTs with bottom-gate top-contacted configuration are further fabricated on a flexible polyimide substrate with the Al_(2)O_(3)/HfO_(2) nanolaminates.Benefited from the unique structural and compositional configuration in the nanolaminates consisting of amorphous Al_(2)O_(3),crystallized HfO_(2),and the aluminate Al-Hf-O phase,the as-prepared TFTs present the carrier mobilities of 9.7 cm^(2) V^(−1) s^(−1),ON/OFF ratio of-1.3×10^(6),subthreshold voltage of 0.1 V,saturated current up to 0.83 mA,and subthreshold swing of 0.256 V dec^(−1),signifying a high-performance flexible TFT,which simultaneously able to withstand the bending radius of 40 mm.The TFTs with nanolaminate insulator possess satisfactory humidity stability and hysteresis behavior in a relative humidity of 60-70%,a temperature of 25-30℃ environment.The yield of IGZO-based TFTs with the nanolaminate insulator reaches 95%.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

Flexible and transparent electronics enters into a new era of electronic technologies.Ubiquitous applications involve wearable electronics,biosensors,flexible transparent displays,radio-frequency identifications（RFIDs）,etc.Zinc oxide（ZnO） and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices,owing to their high electrical performances,together with low processing temperatures and good optical transparencies.In this paper,we review recent advances in flexible and transparent thin-film transistors（TFTs） based on ZnO and relevant materials.After a brief introduction,the main progress of the preparation of each component（substrate,electrodes,channel and dielectrics） is summarized and discussed.Then,the effect of mechanical bending on electrical performance is highlighted.Finally,we suggest the challenges and opportunities in future investigations.

Influence of Post-Annealing on Electrical Characteristics of Thin-Film Transistors with Atomic-Layer-Deposited ZnO-Channel/Al_2O_3-Dielectric

High-performance thin-film transistors （TFTs） with a low thermal budget are highly desired for flexible electronic applications. In this work, the TFTs with atomic layer deposited ZnO-channel/Al2O3-dielectric are fabricated under the maximum process temperature of 200℃. First, we investigate the effect of post-annealing environment such as N2, H2-N2 （4%） and O2 on the device performance, revealing that o2 annealing can greatly enhance the device performance. Further, we compare the influences of annealing temperature and time on the device performance. It is found that long anneMing at 200℃is equivalent to and even outperforms short annealing at 300℃. Excellent electrical characteristics of the TFTs are demonstrated after 02 anneMing at 200℃ for 35 rain, including a low off-current of 2.3 × 10-13 A, a small sub-threshold swing of 245 m V/dec, a large on/off current ratio of 7.6×10s, and a high electron effective mobility of 22.1cm2/V.s. Under negative gate bias stress at -10 V, the above devices show better electrical stabilities than those post-annealed at 300℃. Thus the fabricated high-performance ZnO TFT with a low thermal budget is very promising for flexible electronic applications.

Water-based processed and alkoxide-based processed indium oxide thin-film transistors at different annealing temperatures

In this study,indium oxide（In2O3） thin-film transistors（TFTs） are fabricated by two kinds of low temperature solution-processed technologies（Ta ≤ 300℃）,i.e.,water-based（DIW-based） process and alkoxide-based（2-ME-based）process.The thickness values,crystallization properties,chemical structures,surface roughness values,and optical properties of In2O3 thin-films and the electrical characteristics of In2O3 TFTs are studied at different annealing temperatures.Thermal annealing at higher temperature leads to an increase in the saturation mobility（μsat） and a negative shift in the threshold voltage（VTH）.The DIW-based processed In2O3-TFT annealed at 300℃ exhibits excellent device performance,and one annealed at 200℃ exhibits an acceptable μsat of 0.86 cm^2/V·s comparable to that of a-Si：H TFTs,whereas the 2-ME-based TFT annealed at 300℃ exhibits an abundant μsat of 1.65 cm^2/Vs and one annealed at 200℃ is inactive.The results are attributed to the fact that the DIW-based process induces a higher degree of oxidation and less defect states than the 2-ME-based process at the same temperature.The DIW-based process for fabricating the In2O3 TFT opens the way for the development of nontoxic,low-cost,and low-temperature oxide electronics.

Electrical properties of zinc-oxide-based thin-film transistors using strontium-oxide-doped semiconductors

Strontium-zinc-oxide（SrZnO） films forming the semiconductor layers of thin-film transistors（TFTs） are deposited by using ion-assisted electron beam evaporation. Using strontium-oxide-doped semiconductors, the off-state current can be dramatically reduced by three orders of magnitude. This dramatic improvement is attributed to the incorporation of strontium, which suppresses carrier generation, thereby improving the TFT. Additionally, the presence of strontium inhibits the formation of zinc oxide（ZnO） with the hexagonal wurtzite phase and permits the formation of an unusual phase of ZnO, thus significantly changing the surface morphology of ZnO and effectively reducing the trap density of the channel.

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can recover in a short time.After comparing with the degradation phenomena under negative bias illumination stress(NBIS),positive bias stress(PBS),and positive bias illumination stress(PBIS),degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies(V_(o)^(+))in addition to the commonly reported doubly charged oxygen vacancies(V_(o)^(2+)).Furthermore,the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of V_(o)^(+)under positive gate bias.The proposed degradation mechanisms are verified by TCAD simulation.

Study on characteristics of a double-conductible channel organic thin-film transistor with an ultra-thin hole-blocking layer

The properties of top-contact organic thin-film transistors （TC-OTFTs） using ultra-thin 2, 9-dimethyl-4, 7- diphenyl-1, 10-phenanthroline （BCP） as a hole-blocking interlayer have been improved significantly and a BCP interlayer was inserted into the middle of the pentacene active layer. This paper obtains a fire-new transport mode of an OTFT device with double-conductible channels. The accumulation and transfer of the hole carriers arc limited by the BCP interlayer in the vertical region of the channel. A huge amount of carriers is located not only at the interface between pentacene and the gate insulator, but also at the two interfaces of pentacene/BCP interlayer and pentacene/gate insulator, respectively. The results suggest that the BCP interlayer may be useful to adjust the hole accumulation and transfer, and can increase the hole mobility and output current of OTFTs. The TC-OTFTs with a BCP interlayer at VDS = --20 V showed excellent hole mobility μFE and threshold voltage VTH of 0.58 cm^2/（V-s） and -4.6 V, respectively.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress(NBS)reliability of n-type polycrystalline silicon(poly-Si)thin-film transistors(TFTs)with a distinct defective grain boundary(GB)in the channel is investigated.Results show that conventional NBS degradation with negative shift of the transfer curves is absent.The on-state current is decreased,but the subthreshold characteristics are not affected.The gate bias dependence of the drain leakage current at V_(ds)of 5.0 V is suppressed,whereas the drain leakage current at V_(ds)of 0.1 V exhibits obvious gate bias dependence.As confirmed via TCAD simulation,the corresponding mechanisms are proposed to be trap state generation in the GB region,positive-charge local formation in the gate oxide near the source and drain,and trap state introduction in the gate oxide.