Dynamic modeling of total ionizing dose-induced threshold voltage shifts in MOS devices

The total ionizing dose(TID) effect is a key cause for the degradation/failure of semiconductor device performance under energetic-particle irradiation. We developed a dynamic model of mobile particles and defects by solving the rate equations and Poisson's equation simultaneously, to understand threshold voltage shifts induced by TID in silicon-based metal–oxide–semiconductor(MOS) devices. The calculated charged defect distribution and corresponding electric field under different TIDs are consistent with experiments. TID changes the electric field at the Si/SiO_(2) interface by inducing the accumulation of oxide charged defects nearby, thus shifting the threshold voltage accordingly. With increasing TID, the oxide charged defects increase to saturation, and the electric field increases following the universal 2/3 power law. Through analyzing the influence of TID on the interfacial electric field by different factors, we recommend that the radiation-hardened performance of devices can be improved by choosing a thin oxide layer with high permittivity and under high gate voltages.

Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node

Threshold voltage (VTH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise VTH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.

Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation

A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD simulation.Comparisons were carried out between conventional VNWFET and the proposed devices.FD-SOI-HC VNWFET exhibits better Ion/Ioff ratio and DIBL than Bulk-HC VNWFET.The impact of channel doping and geometric parameters on the electrical character-istic and body factor(γ)of the devices was investigated.Moreover,threshold voltage modulation by bulk/back-gate bias was im-plemented and a largeγis achieved for wide range V_(th)modulation.In addition,results of I_(on)enhancement and Ioff reduction in-dicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management.The results of preliminary experimental data are discussed as well.

Effect of X-ray irradiation on threshold voltage of AlGaN/GaN HEMTs with p-GaN and MIS Gates

Commercially available AlGaN/GaN high-electron-mobility transistors(HEMTs)are beginning to enter the public scene froma range of suppliers.Based on previous studies,commercial GaN-based electronics are expected to be tolerant to different types of irradiation in space.To test this assumption,we compared the characteristic electrical curves obtained at different X-ray irradiation doses for GaN HEMT devices manufactured by Infineon and Transphorm.The p-GaN-based device was found to be more robust with a stable threshold voltage,whereas the threshold voltage of the device with ametal-insulator-semiconductor gatewas found to shift first in the negative and then the positive direction.This dynamic phenomenon is caused by the releasing and trapping effects of radiation-induced charges in the dielectric layer and at the interface of irradiated devices.As such,the p-GaNgate-based GaN HEMT provides a promising solution for use as an electric source in space.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.

The effect of substrate doping on the flatband and threshold voltages of a strained-Si pMOSFET

The effect of substrate doping on the flatband and threshold voltages of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor（pMOSFET） has been studied.By physically deriving the models of the flatband and threshold voltages,which have been validated by numerical simulation and experimental data,the shift in the plateau from the inversion region to the accumulation region as the substrate doping increases has been explained.The proposed model can provide a valuable reference to the designers of strained-Si devices and has been implemented in software for extracting the parameters of a strained-Si MOSFET.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.

Characteristics and threshold voltage model of GaN-based FinFET with recessed gate

In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

Directly extracting both threshold voltage and series resistance from the conductance-voltage curve of an AlGaN/GaN Schottky diode

An Ni/Au Schottky contact on an AlGaN/GaN heterostructure has been prepared. By using the peak-conductance model, the threshold voltage and the series resistance of the AlGaN/GaN diode are simultaneously extracted from the conductance-voltage （G-V） curve and found to be in good agreement with the ones obtained by using the capacitance-voltage （C-V） curve integration and the plot of dV/d（ln I） versus current I. Thus, a method of directly and simultaneously extracting both the threshold voltage and the series resistance from the conductance-voltage curve for the AlGaN/GaN Schottky diode is developed.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.

Migration of weakly bonded oxygen atoms in a-IGZO thin films and the positive shift of threshold voltage in TFTs

Amorphous indium-gallium-zinc oxide(a-IGZO)thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor(TFT)devices.In-situ x-ray photoelectron spectroscopy(XPS)illustrates that weakly bonded oxygen(O)atoms exist in a-IGZO thin films deposited at high O_(2) pressures,but these can be eliminated by vacuum annealing.The threshold voltage(V_(th))of the a-IGZO TFTs is shifted under positive gate bias,and the Vth shift is positively related to the deposition pressure.A temperature variation experiment in the range of 20 K-300 K demonstrates that an activation energy of 144 meV is required for the Vth shift,which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films.Accordingly,the Vth shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO_(2) interface under positive gate bias.These results provide an insight into the mechanism responsible for the Vth shift of the a-IGZO TFTs and help in the production of reliable designs.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs

Threshold voltage (V_(TH)) hysteresis affects the dynamic characteristics of silicon carbide (SiC) MOSFETs, whichin turn affects reliability of a device. In this paper, a dynamichysteresis curve is proposed as an evaluation method of theinfluence of V_(TH) hysteresis on the switching characteristics ofSiC MOSFETs. This method can eliminate the impact of triggerlevel and obtain the dynamic V_(TH). Furthermore, the influence ofparasitic parameters on dynamic V_(TH) hysteresis is theoreticallyanalyzed. Double pulse tests under different parasitic parametersare performed on three SiC MOSFETs with different gatestructures to verify the analysis. Results show that gate resistance(R_(G)) and source inductance (L_(S)) have more significant effectson dynamic V_(TH) hysteresis compared with gate inductance anddrain inductance. V_(TH) hysteresis phenomenon weakens withincrease of R_(G) or L_(S), which is related to device structure.The results presented in this paper can provide guidance forthe design of circuit parasitic parameters of SiC MOSFETs toregulate V_(TH) hysteresis.

Low threshold voltage light-emitting diode in silicon-based standard CMOS technology

Low-voltage silicon （Si）-based light-emitting diode （LED） is designed based on the former research of LED in Si-based standard complementary metal oxide semiconductor （CMOS） technology. The low-voltage LED is designed under the research of cross-finger structure LEDs and sophisticated structure enhanced LEDs for high efficiency and stable light source of monolithic chip integration. The device size of low-voltage LED is 45.85x38.4 （#m）, threshold voltage is 2.2 V in common condition, and temperature is 27 ~C. The external quantum efficiency is about 10-6 at stable operating state of 5 V and 177 mA.

Suppressed threshold voltage roll-off and ambipolar transport in multilayer transition metal dichalcogenide feed-back gate transistors

The layered semiconducting transition metal dichaloogenides(S-TMDs)have attracted considerable interest as the channel material for field-effect transistors(FETs).However,the multilayer S-TMD transistors usually exhibit considerable threshold voltage(Vn)shit and ambipolar behavior at high source-drain bias,which is undesirable for modern digital electronics.Here we report the design and fabrication of double feedback gate(FBG)transistors,i.e.,source FBG(S-FBG)and drain FBG(D-FBG),to combat these challenges.The FBG transistors differ from normal transistors by including an extra feedback gate,which is directly connected t0 the source/drain electrodes by extending and overlapping the source/drain electrodes over the yttrium oxide dielectrics on s-TMDs.We show that the S-FBG transistors based on mutilayer MoSg exhibit nearly negligible VIn rlloff at large source drain bias,and the D-FBG mutilayer WSe2 transistors could be tailored into either n-type or p-type transport,depending on the polarity of the drain bias.The double FBG structure offers an effective strategy to tailor multilayer s-TMD transistors with suppressed Vn roll-off and ambipolar transport for high-performance and low-power logic applications.

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson＇s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.