A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of therm...A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermalstress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results（＆lt; ±5%）. The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC, leading to the more accurate timing analysis considering the thermal-stress effect.展开更多
A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,...A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,110μm wide vias in silicon.The wafer-level filling process can be completed in a few seconds,which is much faster than using the traditional electroplating process.Thermo-mechanical analysis of via filling using solder,Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials.It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.展开更多
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical ...Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.展开更多
To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The c...To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.展开更多
In this paper, a new type of through-silicon via（TSV） for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technolo...In this paper, a new type of through-silicon via（TSV） for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types： bare signal TSVs and bare ground TSVs. First, by solving Poisson＇s equation for cylindrical P–N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design,routing and placement can be retained after the application of the bare TSVs.展开更多
In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a...In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.展开更多
基金supported by the Aerospace Advanced Manufacturing Technology Research Joint Fund(No.U1537208)
文摘A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermalstress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results（＆lt; ±5%）. The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC, leading to the more accurate timing analysis considering the thermal-stress effect.
基金Project supported by the National S & T Major Projects(Nos.2009ZX02038,2011ZX02709)the 100 Talents Programme of the Chinese Academy of Sciences
文摘A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture.Cu-cored solder balls with a total diameter of 100μm were used to fill 150μm deep,110μm wide vias in silicon.The wafer-level filling process can be completed in a few seconds,which is much faster than using the traditional electroplating process.Thermo-mechanical analysis of via filling using solder,Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials.It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
文摘Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
基金supported by the National Natural Science Foundation of China(No.61422402)the Tsinghua University Initiative Scientific Research Program
文摘To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.
基金Project supported by the National Basic Research Program of China (No. 2015CB0572)the Importation and Development of HighCaliber Talents Project of Beijing Municipal Institutions (No. CIT&TCD20150320)the National Natural Science Foundation of China (No. 61176102)
文摘In this paper, a new type of through-silicon via（TSV） for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types： bare signal TSVs and bare ground TSVs. First, by solving Poisson＇s equation for cylindrical P–N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design,routing and placement can be retained after the application of the bare TSVs.
基金supported by the National Key Research and Development Program of China(2021YFB2011700).
文摘In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
