The high-intensity heavy-ion accelerator facility(HIAF)is a scientific research facility complex composed of multiple cas-cade accelerators of different types,which pose a scheduling problem for devices distributed ov...The high-intensity heavy-ion accelerator facility(HIAF)is a scientific research facility complex composed of multiple cas-cade accelerators of different types,which pose a scheduling problem for devices distributed over a certain range of 2 km,involving over a hundred devices.The white rabbit,a technology-enhancing Gigabit Ethernet,has shown the capability of scheduling distributed timing devices but still faces the challenge of obtaining real-time synchronization calibration param-eters with high precision.This study presents a calibration system based on a time-to-digital converter implemented on an ARM-based System-on-Chip(SoC).The system consists of four multi-sample delay lines,a bubble-proof encoder,an edge controller for managing data from different channels,and a highly effective calibration module that benefits from the SoC architecture.The performance was evaluated with an average RMS precision of 5.51 ps by measuring the time intervals from 0 to 24,000 ps with 120,000 data for every test.The design presented in this study refines the calibration precision of the HIAF timing system.This eliminates the errors caused by manual calibration without efficiency loss and provides data support for fault diagnosis.It can also be easily tailored or ported to other devices for specific applications and provides more space for developing timing systems for particle accelerators,such as white rabbits on HIAF.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device....A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.展开更多
A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is perform...A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is performed by the coarse counter and fine interpolator,which are utilized to measure the total periods and the residue time of the reference clock,respectively.Following a detail analysis of time precision and clock jitter in the two-step structure,the prototype TDC fabricated in GSMC 1P6M 0.18μm CMOS Image Sensor(CIS)technology exhibits a Single-Shot Precision(SSP)of 11.415 ps and a dynamic range of 216.7 ns.In addition,a pixel of the chip occupies 100μm×100μm,and the measured Integral Nonlinearity(INL)and Differential Nonlinearity(DNL)are better than±0.88 LSB and±0.67 LSB,respectively.Meanwhile,the overall power consumption of the chip is 35 mW at 1.8 V power supply.Combined with these characteristics,the designed chip is suitable for TOF-based ranging applications.展开更多
This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to d...This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.展开更多
在精密时频测控领域中,高分辨率、无死区的时间间隔和频率测量非常关键,而时间数字转换器(Time to Digital Converter,TDC)是时间频率测量的常用手段。该文研制了基于ACAM公司生产的时间数字转换芯片TDC-GP21和Altera公司FPGA芯片EP4CE6...在精密时频测控领域中,高分辨率、无死区的时间间隔和频率测量非常关键,而时间数字转换器(Time to Digital Converter,TDC)是时间频率测量的常用手段。该文研制了基于ACAM公司生产的时间数字转换芯片TDC-GP21和Altera公司FPGA芯片EP4CE6E22C8N的时间频率测量设备,实现了高分辨率的时间间隔测量,测量分辨率达到13ps。同时采用时间间隔测量模块两两组合的方式实现了无死区频率测量,创新性地采用每组3个TDC芯片,共4组搭建了时间频率测量系统,并对组内3个TDC芯片测量结果采用平均值滤波法,使频率测量稳定度达到1.1 ×10^(-11)@1 s,5.6 × 10^(-15)@10000 s,与商用K+K FXE频率计数器指标相当。本设备具有体积小、无需校准、成本低等优点,能够广泛应用到高精度时间间隔和精密频率测量领域中。展开更多
基金supported by high-intensity heavy-ion accelerator facility(HIAF)approved by the National Development and Reform Commission of China(2017-000052-73-01-002107)。
文摘The high-intensity heavy-ion accelerator facility(HIAF)is a scientific research facility complex composed of multiple cas-cade accelerators of different types,which pose a scheduling problem for devices distributed over a certain range of 2 km,involving over a hundred devices.The white rabbit,a technology-enhancing Gigabit Ethernet,has shown the capability of scheduling distributed timing devices but still faces the challenge of obtaining real-time synchronization calibration param-eters with high precision.This study presents a calibration system based on a time-to-digital converter implemented on an ARM-based System-on-Chip(SoC).The system consists of four multi-sample delay lines,a bubble-proof encoder,an edge controller for managing data from different channels,and a highly effective calibration module that benefits from the SoC architecture.The performance was evaluated with an average RMS precision of 5.51 ps by measuring the time intervals from 0 to 24,000 ps with 120,000 data for every test.The design presented in this study refines the calibration precision of the HIAF timing system.This eliminates the errors caused by manual calibration without efficiency loss and provides data support for fault diagnosis.It can also be easily tailored or ported to other devices for specific applications and provides more space for developing timing systems for particle accelerators,such as white rabbits on HIAF.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
基金Supported by the National High Technology Research and Development Program(No.2012AA121901)
文摘A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.
基金National Natural Science Foundation of China(61774129,61827812,61704145)Hunan Science and Technology Department Huxiang High-level Talent Gathering Project(2019RS1037)Changsha Science and Technology Plan Key Projects(kq1801035)。
文摘A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is performed by the coarse counter and fine interpolator,which are utilized to measure the total periods and the residue time of the reference clock,respectively.Following a detail analysis of time precision and clock jitter in the two-step structure,the prototype TDC fabricated in GSMC 1P6M 0.18μm CMOS Image Sensor(CIS)technology exhibits a Single-Shot Precision(SSP)of 11.415 ps and a dynamic range of 216.7 ns.In addition,a pixel of the chip occupies 100μm×100μm,and the measured Integral Nonlinearity(INL)and Differential Nonlinearity(DNL)are better than±0.88 LSB and±0.67 LSB,respectively.Meanwhile,the overall power consumption of the chip is 35 mW at 1.8 V power supply.Combined with these characteristics,the designed chip is suitable for TOF-based ranging applications.
文摘This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.
文摘在精密时频测控领域中,高分辨率、无死区的时间间隔和频率测量非常关键,而时间数字转换器(Time to Digital Converter,TDC)是时间频率测量的常用手段。该文研制了基于ACAM公司生产的时间数字转换芯片TDC-GP21和Altera公司FPGA芯片EP4CE6E22C8N的时间频率测量设备,实现了高分辨率的时间间隔测量,测量分辨率达到13ps。同时采用时间间隔测量模块两两组合的方式实现了无死区频率测量,创新性地采用每组3个TDC芯片,共4组搭建了时间频率测量系统,并对组内3个TDC芯片测量结果采用平均值滤波法,使频率测量稳定度达到1.1 ×10^(-11)@1 s,5.6 × 10^(-15)@10000 s,与商用K+K FXE频率计数器指标相当。本设备具有体积小、无需校准、成本低等优点,能够广泛应用到高精度时间间隔和精密频率测量领域中。
