基于直线电机驱动的恒增力杠杆与二次正交toggle机构的压紧装置

基于杆件可重构的理念,创新设计了2种直线电机驱动的基于杠杆及二次正交toggle增力机构的压紧装置,对其工作原理进行了分析,并给出了相应的力学计算公式。该压紧装置可满足不同结构尺寸及位置的要求,适应了压紧装置绿色化的发展趋势,具有较广阔的应用前景。

支持ONFI和Toggle模式的NAND Flash PHY设计

论文设计了一种能支持ONFI 2.1与Toggle 1.0模式的NAND Flash PHY,完成了其读写通道、地址与控制逻辑的设计,并采用读门控电路消除DQS读前后的毛刺。功能仿真与静态时序分析结果表明,PHY的设计达到了ONFI与Toggle标准时序要求。NAND Flash PHY面积为45245.5μm2,动态功耗为1.16mW,静态功耗为95.8μW。

高帽变换和toggle算子组合的图像增强优化算法

针对灰度图像对比度较低而难以识别目标区域的问题,对形态学中传统的高帽变换算子和toggle算子进行组合,提出了基于高帽变换和toggle算子组合的图像增强优化算法。该算法利用高帽变换算子增大原始图像灰度值的动态范围,同时利用toggle算子锐化图像,使图像清晰。实验结果表明,该组合算子相对单个算子来说,对灰度图像的对比度增强效果更好,目标识别效果更佳。

对称之美——气动肌腱驱动的基于三级toggle增力机构的压力机

利用直径不同的两只气动肌腱与三级toggle增力机构进行巧妙的对称组合,创新设计了一种新型的气动肌腱驱动的基于三级toggle增力机构的压力机,对其工作原理进行了分析,并给出了相应的力学计算公式。该压力机的大直径气动肌腱用于压头的工作行程,而小直径气动肌腱用于压头的返回行程。该压力机适应了绿色化的发展趋势,具有广阔的应用前景。

Stability and Flipping Dynamics of Delayed Genetic Toggle Switch

A detailed analysis of the stability and flipping dynamics of a delayed exclusive toggle switch is performed. We use forward flux sampling method combined with delayed stochastic simulation algorithm to get the stationary distribution function, the switching rate, and path- ways, as well as the transition state ensemble. Interestingly, under the influence of time delay, the stationary distribution corresponding to the stable states become narrower and the population in the transition region is significantly enhanced. In addition, the flipping rate increases monotonically with delay. Such findings demonstrate that time delay could reduce the stability of the bistable genetic switch dramatically. Furthermore, the transition pathways, characterized by the difference in the protein numbers and the state of operator, show larger discrepancy between the forward and backward switching process with increas- ing delay, indicating that transcriptional and translational delay can remarkably affect the flipping dynamics. Specifically, for the transition state, the difference in the probability of finding the operator site bound by the two different protein dimers is enlarged by delay, which further illustrates the crucial role of time delay on the stability and switching dynamics of genetic toggle switches.

The Neuron as a Controlled Toggle Circuit

This paper considers a model of a recursive neuron whose circuit the author finds interesting, not because of its financial possibility, but because of its surprising electrical behavior. Below, a recursive neuron is modeled with excitatory and inhibitory triggering, and simulated using Win Spice. This model is shown to be capable of controlled toggling, and so promises energy-efficient, massively parallel computing.

Toggle软件全家福

视窗Windows95的推出,改变了计算机传统的操作模式。我们在领略操作系统强大功能的同时,感受更多的恐怕就是它的简单易学和方便快捷,甚至一个3岁小孩都可以在几分钟之内迅速学会计算机的操作方法。MicroSoft的软件精英们确实为用户提供了一种接近计算机的最简捷的途径。尽管如此。

Structure and design method for pulse-triggered flip-flops at switch level

A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed,which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are needed to eliminate the switching activities of internal nodes.Based on the proposed structure and design technique,two pulsed flip-flops were implemented and simulated.The proposed pulsed flip-flops have simple circuit structures.HSPICE simulation shows that the proposed pulsed D flip-flop outperforms the conventional pulsed D flip-flop by 17.2% in delay and 30.1% in power-delay-product(PDP) and the proposed pulsed JK flip-flop has low power and small PDP compared with pulsed D pulsed flip-flops,confirming that the proposed structure and design technique are simple and practical.

DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS

By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter.

A FAULT DETECTION SENSOR FOR CIRCUIT AGING USING DOUBLE-EDGE-TRIGGERED FLIP-FLOP

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Dou- ble-edge-triggered Detection Sensor for circuit Aging （DSDA） is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not case of the detection precision is more than 80% under aging fault effectively with the 8% power cost and 30% sensitive to the process variations. The worst the different process variations. It can detect performance cost.

On Switching of a Flip-Flop Jet Nozzle with Double Ports by Single-Port Control

This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements are carried out varying: 1) the inside diameter d of the connecting tube;2) the length L of the connecting tube and 3) the jet velocity VPN from a primary-nozzle exit. We assume that the jet switches when a time integral reaches a certain value. At first, as the time integral, we introduce the accumulated flow work of pressure, namely, the time integral of mass flux through a connecting tube into the jet-reattaching wall from the opposite jet-un-reattaching wall. Under the assumption, the trace of pressure difference between both the ends of the connecting tube is simply modeled on the basis of measurements, and the flow velocity in the connecting tube is computed as incompressible flow. Second, in order to discuss the physics of the accumulated flow work further, we conduct another experiment in single-port control where the inflow from the control port on the jet-reattaching wall is forcibly controlled and the other control port on the opposite jet-un-reattaching wall is sealed, instead of the experiment in regular jet’s oscillation using the ordinary nozzle with two control ports in connection. As a result, it is found that the accumulated flow work is adequate to determine the dominant jet- oscillation frequency. In the experiment in single-port control, the accumulated flow work of the inflow until the jet’s switching well agrees with that in regular jet’s oscillation using the ordinary nozzle.

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.

Low power and high speed explicit-pulsed double-edge triggered level converting flip-flop

Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.

DESIGN OF TERNARY FLIP-FLOPS AND SEQUENTIAL CIRCUITS BASED UPON U_h GATE

According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies(Invited paper)

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.

Flip-Flop Flow Control inside Streamwise Diverging Diamond-Shaped Cylinder Bundles with Concavities

The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity constructed on both side-walls of a diamond cylinder induces a substantial change in the flow patterns in the exit jet-stream field and jet- stream dispersion, 2) pressure characteristics are quantitatively measured in a diverging-flow region in diamond cylinder bundles with concavityand in its downstream region, and 3) flip-flop flow occurs in the flow passages and its occurrence condition is obtained.

Numerical Simulation of an All Optical Flip-Flop Based on a Nonlinear Distributed Bragg Reflector Laser Structure

A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a negative nonlinear coefficient that is due to direct absorption at Urbach tail. At low light intensity in the structure, the detuned Bragg reflector does not provide optical feedback to start a laser mode. An optical pulse injected to the structure reduces the detuning of the nonlinear Bragg reflector and a laser mode builds up. The device is reset by detuning the second Bragg reflector optically by an optical pulse that generates electron-hole pairs by direct absorption. A mathematical model of the device is introduced. The model is solved numerically in time domain using a general purpose graphics processing unit (GPGPU) to increase accuracy and to reduce the computation time. The switching dynamics of the device are in nanosecond time scale. The device could be used for all optical data packet switching/routing.

An Improved Design for an All-Optical Flip-Flop Based on a Nonlinear 3-Sections DFB Laser Cavity

A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into an active layer provides optical gain to the laser mode. The wave-guiding layer consists of a linear grating section centered between 2 detuned nonlinear grating sections. The average refractive index in the nonlinear sections is slightly higher than the refractive index of the middle section. A negative nonlinear refractive index coefficient exists along the nonlinear sections. In the “OFF” state, the DFB structure does not provide enough optical feedback to lase due to the detuned sections. At high light intensity in structure, “ON” state, detuning decreases and the DFB structure allows for a laser mode that sustains the decrease in detuning to exist. The nonlinearity is provided by direct photon absorption at the Urbach tail. Numerical simulations using GPGPU computing show nanoseconds transition times between “OFF” and “ON” states.

Simulations of a Novel All-Optical Flip-Flop Based on a Nonlinear DFB Laser Cavity Using GPGPU Computing

A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the grating and has negative nonlinear coefficient. Optical gain is provided by an injected electrical current into an active layer. In the OFF state, due to the detuned section, no laser light is generated in the device. An injected optical pulse reduces the detuning of the nonlinear section, and the optical feedback provided by the DFB structure generates a laser light in the structure that sustains the change in the detuned section. The device is switched “OFF” by detuning another section of the grating by a Reset pulse. The Reset pulse reduces the refractive index of that section by the generation of electron-hole pairs. The Reset pulse wavelength is adjusted such that the optical gain provided by the active layer at that wavelength is zero. The Reset pulse is prevented from reaching the nonlinear detuned section by introducing an optical absorber in the laser cavity to attenuate the pulse. The device is simulated in time domain using General Purpose Graphics Processing Unit (GPGPU) computing. Set-Reset operations are in nanosecond time scale.