Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltag...Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.展开更多
A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxi...A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxide locates holes in the top interface of the upper buried oxide （UBO） layer. Furthermore, holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide （LBO） layer. Consequently, the electric fields in both the thin LBO and the thick UBO are enhanced by these holes, leading to an improved breakdown voltage. The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer. Moreover, SBO CBL SOI can also reduce the self-heating effect.展开更多
A new SOI (Silicon On Insulator) high voltage device with Step Unmovable Surface Charges (SUSC) of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented...A new SOI (Silicon On Insulator) high voltage device with Step Unmovable Surface Charges (SUSC) of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson's equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF (REduce SURface Field) condition of the SOI device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3μm-thick top Si layer, 2μm-thick buried oxide layer and 70μum-length drift region using a linear doping profile of unmovable buried oxide charges.展开更多
An approximate analytical model for calculating the pull-in voltage of a stepped cantilever-type radio frequency （RF） micro electro-mechanical system （MEMS） switch is developed based on the Euler-Bernoulli beam an...An approximate analytical model for calculating the pull-in voltage of a stepped cantilever-type radio frequency （RF） micro electro-mechanical system （MEMS） switch is developed based on the Euler-Bernoulli beam and a modified couple stress theory, and is validated by comparison with the finite element results. The sensitivity functions of the pull-in voltage to the designed parameters are derived based on the proposed model. The sensitivity investigation shows that the pull-in voltage sensitivities increase/decrease nonlinearly with the increases in the designed parameters. For the stepped cantilever beam, there exists a nonzero optimal dimensionless length ratio, where the pull-in voltage is insensitive. The optimal value of the dimensionless length ratio only depends on the dimensionless width ratio, and can be obtained by solving a nonlinear equation. The determination of the designed parameters is discussed, and some recommendations are made for the RF MEMS switch optimization.展开更多
A set of seven single junction thermal converter Micropotentiometers (μPots) has been constructed at the National Institute for Standards (NIS), Egypt. This set has been built to cover the low ac voltage ranges from ...A set of seven single junction thermal converter Micropotentiometers (μPots) has been constructed at the National Institute for Standards (NIS), Egypt. This set has been built to cover the low ac voltage ranges from 2 mV to 200 mV at frequencies from 40 Hz up to 20 kHz. The construction of the μPots set has been presented and an adopted calibration method has been performed as well. This method has been performed by means of a step-down procedure using a Digital Multi-Meter (DMM). The scaling procedures have been carried out in sequential steps starting from the calibration of the 200 mV-μpot by using DMM that is accurately calibrated at its 200 mV ac voltage range down to 2 mV-μPot. Furthermore, a new automatic calibration system has been established to achieve the scaling procedures. This system has been specially designed using Laboratory Virtual Instrument Engineering Workbench (LabVIEW) software to overcome the deficiencies of manual methods. The automatic calibration has been investigated of all mPots at different frequencies. The ac-dc differences for the μPots and their uncertainty evaluation from 2 mV to 200 mV at different frequencies from 40 Hz to 20 kHz have been determined.展开更多
基金Project supported partially by the National Natural Science Foundation of China (Grant Nos. 60906038 and 61076082)
文摘Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.
基金Project supported by the National Natural Science Foundation of China (Grant Nos.60806025 and 60976060)in part by the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No.CXJJ201004)
文摘A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxide locates holes in the top interface of the upper buried oxide （UBO） layer. Furthermore, holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide （LBO） layer. Consequently, the electric fields in both the thin LBO and the thick UBO are enhanced by these holes, leading to an improved breakdown voltage. The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer. Moreover, SBO CBL SOI can also reduce the self-heating effect.
基金Supported by the National Natural Science Foundation of China (No.60276040).
文摘A new SOI (Silicon On Insulator) high voltage device with Step Unmovable Surface Charges (SUSC) of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson's equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF (REduce SURface Field) condition of the SOI device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3μm-thick top Si layer, 2μm-thick buried oxide layer and 70μum-length drift region using a linear doping profile of unmovable buried oxide charges.
基金supported by the National Natural Science Foundation of China(Nos.51505089 and61204116)the Opening Project of the Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory(Nos.ZHD201207 and 9140C030605140C03015)the Pearl River S&T Nova Program of Guangzhou(No.2014J2200086)
文摘An approximate analytical model for calculating the pull-in voltage of a stepped cantilever-type radio frequency （RF） micro electro-mechanical system （MEMS） switch is developed based on the Euler-Bernoulli beam and a modified couple stress theory, and is validated by comparison with the finite element results. The sensitivity functions of the pull-in voltage to the designed parameters are derived based on the proposed model. The sensitivity investigation shows that the pull-in voltage sensitivities increase/decrease nonlinearly with the increases in the designed parameters. For the stepped cantilever beam, there exists a nonzero optimal dimensionless length ratio, where the pull-in voltage is insensitive. The optimal value of the dimensionless length ratio only depends on the dimensionless width ratio, and can be obtained by solving a nonlinear equation. The determination of the designed parameters is discussed, and some recommendations are made for the RF MEMS switch optimization.
文摘A set of seven single junction thermal converter Micropotentiometers (μPots) has been constructed at the National Institute for Standards (NIS), Egypt. This set has been built to cover the low ac voltage ranges from 2 mV to 200 mV at frequencies from 40 Hz up to 20 kHz. The construction of the μPots set has been presented and an adopted calibration method has been performed as well. This method has been performed by means of a step-down procedure using a Digital Multi-Meter (DMM). The scaling procedures have been carried out in sequential steps starting from the calibration of the 200 mV-μpot by using DMM that is accurately calibrated at its 200 mV ac voltage range down to 2 mV-μPot. Furthermore, a new automatic calibration system has been established to achieve the scaling procedures. This system has been specially designed using Laboratory Virtual Instrument Engineering Workbench (LabVIEW) software to overcome the deficiencies of manual methods. The automatic calibration has been investigated of all mPots at different frequencies. The ac-dc differences for the μPots and their uncertainty evaluation from 2 mV to 200 mV at different frequencies from 40 Hz to 20 kHz have been determined.
