An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input vol...An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp(peak to peak), whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.展开更多
A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control ...A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.展开更多
A complementary metal oxide semiconductor （CMOS） transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with c...A complementary metal oxide semiconductor （CMOS） transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion （THD） for a 1-MHz 0.4-Vp-p differential input signal. The third-order intermodulation is less than -63 dB for 0.25 Vp-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.展开更多
A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend bot...A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend both the signal input range and the tuning capability. The effective transconductance of the body-driven triode stage is increased using a partial positive feedback technique which also partially solves the problem introduced by the small transconductance. This design uses the UMC 0.18 μm CMOS process. Simulations show the transconductor operated with 1 V supply voltage has less than -55 dB total harmonic distortions （THD） in the complete tuning range （0 V≤ Vcont≤ 0.43 V） for a 1 MHz 0.8 Vp-p differential input. The power consumption is 70 μW for a 0.43 V control voltage.展开更多
宽禁带WBG(wide band gap)半导体电力电子器件由于其开关频率高、开关速度快、寄生参数大等特点从噪声源头引发了越来越严峻的电磁干扰问题。然而,传统的噪声源研究主要集中在30 MHz传导频段以内,如何评估噪声源在30~300 MHz较高频率范...宽禁带WBG(wide band gap)半导体电力电子器件由于其开关频率高、开关速度快、寄生参数大等特点从噪声源头引发了越来越严峻的电磁干扰问题。然而,传统的噪声源研究主要集中在30 MHz传导频段以内,如何评估噪声源在30~300 MHz较高频率范围内的辐射频段产生的影响仍存在不确定性,因此提出1种改进的WBG器件电磁干扰分析模型,与传统的非对称梯形波电磁干扰模型相比,首次详细考虑了WBG器件的结电容和跨导体的非线性特性,评估了非线性参数对辐射频段噪声的影响,并进一步提出该模型在辐射频段噪声源抑制中的应用。仿真结果验证了所提计算方法的准确性,基于SiC器件的硬件测试结果与理论分析相吻合。展开更多
A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.展开更多
基于翻转电压跟随器(Flipped Voltage Follower,FVF)的拓扑结构,实现了一种低功耗高线性的跨导器,跨导值可由控制电压精确改变。运用此跨导单元设计了一种适用于无线收发机系统的多频带Gm-C低通滤波器。该滤波器是由双二次节级联构成的...基于翻转电压跟随器(Flipped Voltage Follower,FVF)的拓扑结构,实现了一种低功耗高线性的跨导器,跨导值可由控制电压精确改变。运用此跨导单元设计了一种适用于无线收发机系统的多频带Gm-C低通滤波器。该滤波器是由双二次节级联构成的六阶巴特沃斯型滤波器,可实现70 k Hz,140 k Hz和210 k Hz多频带选择。采用SMIC 0.18μm CMOS工艺设计的滤波器的线性度IIP3大于22.6 d Bm,在1.8 V电源电压下消耗的功耗为1.37 m W。展开更多
文摘An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp(peak to peak), whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.
文摘A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.
基金Supported by the National High-Tech Research and Development (863) Program of China (No.2006AA01Z224)the National Natural Science Foundation of China (No.90707002)the Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList)
文摘A complementary metal oxide semiconductor （CMOS） transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion （THD） for a 1-MHz 0.4-Vp-p differential input signal. The third-order intermodulation is less than -63 dB for 0.25 Vp-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.
文摘A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend both the signal input range and the tuning capability. The effective transconductance of the body-driven triode stage is increased using a partial positive feedback technique which also partially solves the problem introduced by the small transconductance. This design uses the UMC 0.18 μm CMOS process. Simulations show the transconductor operated with 1 V supply voltage has less than -55 dB total harmonic distortions （THD） in the complete tuning range （0 V≤ Vcont≤ 0.43 V） for a 1 MHz 0.8 Vp-p differential input. The power consumption is 70 μW for a 0.43 V control voltage.
文摘宽禁带WBG(wide band gap)半导体电力电子器件由于其开关频率高、开关速度快、寄生参数大等特点从噪声源头引发了越来越严峻的电磁干扰问题。然而,传统的噪声源研究主要集中在30 MHz传导频段以内,如何评估噪声源在30~300 MHz较高频率范围内的辐射频段产生的影响仍存在不确定性,因此提出1种改进的WBG器件电磁干扰分析模型,与传统的非对称梯形波电磁干扰模型相比,首次详细考虑了WBG器件的结电容和跨导体的非线性特性,评估了非线性参数对辐射频段噪声的影响,并进一步提出该模型在辐射频段噪声源抑制中的应用。仿真结果验证了所提计算方法的准确性,基于SiC器件的硬件测试结果与理论分析相吻合。
文摘A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
文摘基于翻转电压跟随器(Flipped Voltage Follower,FVF)的拓扑结构,实现了一种低功耗高线性的跨导器,跨导值可由控制电压精确改变。运用此跨导单元设计了一种适用于无线收发机系统的多频带Gm-C低通滤波器。该滤波器是由双二次节级联构成的六阶巴特沃斯型滤波器,可实现70 k Hz,140 k Hz和210 k Hz多频带选择。采用SMIC 0.18μm CMOS工艺设计的滤波器的线性度IIP3大于22.6 d Bm,在1.8 V电源电压下消耗的功耗为1.37 m W。
