An Improved Charge Pumping Method to Study Distribution of Trapped Charges in SONOS Memory

In silicon-oxide-nitride-oxide-silicon （SONOS） memory and other charge trapping memories, the charge distribution after programming operation has great impact on the devic＇s characteristics,such as reading,programming/erasing, and reliability. The lateral distribution of injected charges can be measured precisely using the charge pumping method. To improve the precision of the actual measurement, a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side, respectively. Finally, the electron distribution after channel hot electron programming in SONOS memory is obtained,which is close to the drain side with a width of about 50nm.

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET. A 0.12 μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method. The trapped charge distribution with a narrow peak can be precisely characterized with this method, which shows good consistency with the measured threshold voltage.

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.

Effect of trapped charge accumulation on the retention of charge trapping memory

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation. The recombination process between trapped charges is an important issue on the retention of charge trapping memory. Our results show that accumulated trapped holes during P/E cycling can have an influence on retention, and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.

Investigation of heavy ion irradiation effects on a charge trapping memory capacitor by C-V measurement

Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.

High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

Improved charge trapping flash device with Al_2O_3 /HfSiO stack as blocking layer

In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type （MONOS） memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase （P/E） speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.

Total Ionization Dose Effects on Charge Storage Capability of Al2O3/HfO2/Al2O3-Based Charge Trapping Memory Cell

Because of the discrete charge storage mechanism, charge trapping memory（CTM） technique is a good candidate for aerospace and military missions. The total ionization dose（TID） effects on CTM cells with Al2O3/HfO2/Al2O3（AHA） high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage（V（fb））. The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.

Modeling of tunneling current in ultrathin MOS structure with interface trap charge and fixed oxide charge

A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.

Dependence of charge trapping of fluorescent and phosphorescent dopants in organic light-emitting diodes on the dye species and current density

This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping was independent of the current density in devices using fluorescent material as the emitting molecule while this process was exactly opposite when phosphorescent material was used. The triplet-triplet annihilation and dissociation of excitons into free charge carriers was considered to contribute to the decrease in phosphorescent emission under high electric fields. Moreover, the fluorescent dye molecule with a lower energy gap and ionized potential than the host emitter was observed to facilitate the carrier trapping mechanism, and it would produce photon emission.

Charge trapping behavior and its origin in Al_2O_3/SiC MIS system

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

In this work, the trap-assisted tunneling（TAT） mechanism is modeled as a two-step physical process for charge trapping memory（CTM）. The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.

Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory

Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 （HTH） as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 （next to blocking oxide） serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.

Carriers recombination processes in charge trapping memory cell by simulation

We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.

The influence of thermally assisted tunneling on the performance of charge trapping memory

We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.

Enhanced surface-insulating performance of EP composites by doping plasmafluorinated ZnO nanofiller

The surface flashover of epoxy resin(EP) composites is a pivotal problem in the field of highvoltage insulation.The regulation of the interface between the filler and matrix is an effective means to suppress flashover.In this work,nano ZnO was fluorinated and grafted using lowtemperature plasma technology,and the fluorinated filler was doped into EP to study the DC surface flashover performance of the composite.The results show that plasma fluorination can effectively inhibit the agglomeration by grafting –CFxgroups onto the surface of nano-ZnO particles.The fluorine-containing groups at the interface provide higher charge binding traps and enhance the insulation strength at the interface.At the same time,the interface bond cooperation caused by plasma treatment also promoted the accelerating effect of nano ZnO on charge dissipation.The two effects synergistically improve the surface flashover performance of epoxy composites.When the concentration of fluorinated ZnO filler is 20%,the flashover voltage has the highest increase,which is 31.52% higher than that of pure EP.In addition,fluorinated ZnO can effectively reduce the dielectric constant and dielectric loss of epoxy composites.The interface interaction mechanism was further analyzed using molecular dynamics simulation and density functional theory simulation.