Laser-Induced Single Event Transients in Local Oxidation of Silicon and Deep Trench Isolation Silicon-Germanium Heterojunction Bipolar Transistors

We present a study on the single event transient （SET） induced by a pulsed laser in different silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） with the structure of local oxidation of silicon （LOCOS） and deep trench isolation （DTI）. The experimental results are discussed in detail and it is demonstrated that a SiGe HBT with the structure of LOCOS is more sensitive than the DTI SiGe HBT in the SET. Because of the limitation of the DTI structure, the charge collection of diffusion in the DTI SiGe HBT is less than that of the LOCOS SiGe HBT. The SET sensitive area of the LOCOS SiGe HBT is located in the eollector-substrate （C/S） junction, while the sensitive area of the DTI SiGe HBT is located near to the collector electrodes.

Utilizing a shallow trench isolation parasitic transistor to characterize the total ionizing dose effect of partially-depleted silicon-on-insulator input/output n-MOSFETs

we investigate the effects of 60^Co γ-ray irradiation on the 130 nm partially-depleted silicon-on-isolator （PDSOI） input/output （I/O） n-MOSFETs. A shallow trench isolation （STI） parasitic transistor is responsible for the observed hump in the back-gate transfer characteristic curve. The STI parasitic transistor, in which the trench oxide acts as the gate oxide, is sensitive to the radiation, and it introduces a new way to characterize the total ionizing dose （TID） responses in the STI oxide. A radiation enhanced drain induced barrier lower （DIBL） effect is observed in the STI parasitic transistor. It is manifested as the drain bias dependence of the radiation-induced off-state leakage and the increase of the DIBL parameter in the STI parasitic transistor after irradiation. Increasing the doping concentration in the whole body region or just near the STI sidewall can increase the threshold voltage of the STI parasitic transistor, and further reduce the radiation-induced off-state leakage. Moreover, we find that the radiation-induced trapped charge in the buried oxide leads to an obvious front-gate threshold voltage shift through the coupling effect. The high doping concentration in the body can effectively suppress the radiation-induced coupling effect.

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

The effects of gamma irradiation on the shallow trench isolation（STI）leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device＇s gate length.The three-transistor model（one main transistor with two parasitic transistors）can provide us with a brief understanding of the dependence on gate length.

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.

Impact of substrate bias on radiation-induced edge effects in MOSFETs

This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation （STI） leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold region is observed after irradiation, which is considered to be due to the thin STI corner oxide thickness. A negative substrate bias could effectively suppress the STI leakage, but it also impairs the device characteristics. The three-dimensional simulation is introduced to understand the impact of substrate bias, Moreover, we propose a simple method for extracting the best substrate bias value, which not only eliminates the STI leakage but also has the least impact on the device characteristics.

Bias dependence of a deep submicron NMOSFET response to total dose irradiation

Deep submicron n-channel metal-oxide-semiconductor field-effect transistors （NMOSFETs） with shallow trench isolation （STI） are exposed to ionizing dose radiation under different bias conditions. The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case （ON bias） for the transistors are discussed. The high electric fields at the corners are partly responsible for the subthreshold hump effect. Charge trapped in the isolation oxide, particularly at the Si/SiO2 interface along the sidewalls of the trench oxide creates a leakage path, which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET. Non-uniform charge distribution is introduced into a threedimensional （3D） simulation. Good agreement between experimental and simulation results is demonstrated. We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.

Total ionizing dose effect in an input/output device for flash memory

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are exam- ined. The radiation tests are performed at 60Co sources at the dose rate of 50 rad （Si）/s. The investigation＇s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation struc- ture is the main total dose problem. The total ionizing dose （TID） radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is estab- lished. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I V characteristics of 180 nm commer- cial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.

Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

The influence of shallow trench isolation（STI） on a 90 nm polysilicon-oxide-nitride-oxide-silicon structure non-volatile memory has been studied based on experiments.It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably.The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem.In order to mitigate the STI impact,an added boron implantation in the STI region is developed as a new solution.Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells,respectively.The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.

Influence of drain and substrate bias on the TID effect for deep submicron technology devices

This paper presents a study of the total ionization effects of a 0.18 #m technology. The electrical para meters of NMOSFETs were monitored before and after irradiation with 6~Co at several dose levels under different drain and substrate biases. Key parameters such as offstate leakage current and threshold voltage shift were studied to reflect the ionizing radiation tolerance, and explained using a parasitic transistors model. 3D device simulation was conducted to provide a better understanding of the dependence of device characteristics on drain and substrate biases.

Radiation induced inter-device leakage degradation

The evolution of inter-device leakage generation technologies is studied with an N-type current with total ionizing dose in transistors in 180 nm poly-gate field device （PFD） that uses the shallow trench isolation as an effective gate oxide. The overall radiation response of these structures is determined by the trapped charge in the oxide. The impacts of different bias conditions during irradiation on the inter-device leakage current are studied for the first time in this work, which demonstrates that the worst condition is the same as traditional NMOS transistors. Moreover simulation is used to understand the bias dependence the two-dimensional technology computer-aided design

Testing Structure for Detection of Poly Stringer Defects in CMOS ICs

A testing structure was developed to more effectively detect the poly stringer defects in contemporary CMOS ICs. This structure is much more sensitive to poly stringer defects and is closer to the real product layout than the currently widely used structure using an active dummy underneath a poly comb. Many testing structure pieces manufactured in a 0.11 μm copper process line were used to compare the current design with the conventional testing structure. The data shows that the new structure more efficiently detects poly stringers. The results also show that the poly stringers are related to the shallow trench isolation （STI） width. This structure can be used to identify new designs for manufacturing rules for the active space. Thus, this method is very useful for IC foundries to detect poly stringers and to characterize the processing line capability and tune the process recipe to improve product yields.