A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS d...A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.展开更多
The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors（UMOSFETs） is reported in this paper.The device has a 15-μm thick drift layer with 3×10^15 cm^-3 N-type doping c...The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors（UMOSFETs） is reported in this paper.The device has a 15-μm thick drift layer with 3×10^15 cm^-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm^2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage（Vth） is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance（Rsp-on） is 181 mΩ·cm^2 at Vg = 40 V and a blocking voltage（BV） is 880 V（IDS = 100 μA@880V） at Vg = 0 V.展开更多
研究了一种新型4H-Si C U型槽栅金属氧化物半导体场效应晶体管(UMOSFETs)结构.该结构中的p-body区下方有一p型突出屏蔽区.在关态下,该p型突出屏蔽区能够有效的保护栅氧化层,降低栅氧电场,提高击穿电压.在开态下,该p型屏蔽区并没有对器...研究了一种新型4H-Si C U型槽栅金属氧化物半导体场效应晶体管(UMOSFETs)结构.该结构中的p-body区下方有一p型突出屏蔽区.在关态下,该p型突出屏蔽区能够有效的保护栅氧化层,降低栅氧电场,提高击穿电压.在开态下,该p型屏蔽区并没有对器件的电流产生阻碍作用,并没有带来JFET电阻效应,能够有效的降低器件导通电阻.此外,该结构表面还集成了poly Si/Si C异质结二极管,降低了器件的反向恢复电荷,从而改善器件的反向恢复特性.仿真结果显示,与p+-Si C屏蔽区UMOSFET结构比较,该新结构的特征导通电阻降低了53. 8%,反向恢复电荷减小了57. 1%.展开更多
Si C作为第三代半导体材料的代表性材料,具有宽禁带、高临界击穿电场、高电子饱和迁移速率和高导热率等优良特性,使其在电力电子器件领域得到广泛关注。通过采用电感耦合等离子体(ICP)设备对4H-SiC材料进行刻蚀工艺研究。该刻蚀实验采用...Si C作为第三代半导体材料的代表性材料,具有宽禁带、高临界击穿电场、高电子饱和迁移速率和高导热率等优良特性,使其在电力电子器件领域得到广泛关注。通过采用电感耦合等离子体(ICP)设备对4H-SiC材料进行刻蚀工艺研究。该刻蚀实验采用Si O2膜作为刻蚀掩模,SFx/O2作为刻蚀工艺气体,通过一系列工艺参数调整及刻蚀结果分析,得出了ICP源功率、RF偏压功率、氧气流量和腔体压强对Si C材料刻蚀速率、刻蚀选择比以及刻蚀形貌的影响,并得到最优工艺参数。对刻蚀样片进行后处理工艺,获得了底部圆滑、侧壁垂直的沟槽结构,该沟槽结构对4H-SiC功率UMOSFET性能优化起到关键性作用。展开更多
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906048)the Program for New Century Excellent Talents in University,China (Grant No. NCET-10-0052)the Fundamental Research Funds for the Central Universities,China (Grant No. HEUCFT1008)
文摘A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176070 and 61274079)the Doctoral Fund of Ministry of Education of China (Grant No. 20110203110010)the Key Specific Projects of Ministry of Education of China (Grant No. 625010101)
文摘The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors（UMOSFETs） is reported in this paper.The device has a 15-μm thick drift layer with 3×10^15 cm^-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm^2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage（Vth） is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance（Rsp-on） is 181 mΩ·cm^2 at Vg = 40 V and a blocking voltage（BV） is 880 V（IDS = 100 μA@880V） at Vg = 0 V.
