Physical mechanism of secondary-electron emission in Si wafers

CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.

Damage Mechanism of Ultra-thin Asphalt Overlay(UTAO) based on Discrete Element Method

Aiming to analyze the damage mechanism of UTAO from the perspective of meso-mechanical mechanism using discrete element method(DEM),we conducted study of diseases problems of UTAO in several provinces in China,and found that aggregate spalling was one of the main disease types of UTAO.A discrete element model of UTAO pavement structure was constructed to explore the meso-mechanical mechanism of UTAO damage under the influence of layer thickness,gradation,and bonding modulus.The experimental results show that,as the thickness of UTAO decreasing,the maximum value and the mean value of the contact force between all aggregate particles gradually increase,which leads to aggregates more prone to spalling.Compared with OGFC-5 UTAO,AC-5 UTAO presents smaller maximum and average values of all contact forces,and the loading pressure in AC-5 UTAO is fully diffused in the lateral direction.In addition,the increment of pavement modulus strengthens the overall force of aggregate particles inside UTAO,resulting in aggregate particles peeling off more easily.The increase of bonding modulus changes the position where the maximum value of the tangential force appears,whereas has no effect on the normal force.

Regulation of interlayer channels of graphene oxide nanosheets in ultra-thin Pebax mixed-matrix membranes for CO_(2) capture

For the application of carbon capture by membrane process,it is crucial to develop a highly permeable CO_(2)-selective membrane.In this work,we reported an ultra-thin polyether-block-amide(Pebax)mixedmatrix membranes(MMMs)incorporated by graphene oxide(GO),in which the interlayer channels were regulated to optimize the CO_(2)/N_(2) separation performance.Various membrane preparation conditions were systematically investigated on the influence of the membrane structure and separation performance,including the lateral size of GO nanosheets,GO loading,thermal reduction temperature,and time.The results demonstrated that the precisely regulated interlayer channel of GO nanosheets can rapidly provide CO_(2)-selective transport channels due to the synergetic effects of size sieving and preferential adsorption.The GO/Pebax ultra-thin MMMs exhibited CO_(2)/N_(2) selectivity of 72 and CO_(2) permeance of 400 GPU(1 GPU=106 cm^(3)(STP)·cm^(2)·s^(-1)·cmHg^(-1)),providing a promising candidate for CO_(2) capture.

Wafer map defect patterns classification based on a lightweight network and data augmentation

Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capa-bilities.However,most of the current wafer defect patterns classification models have high complexity and slow detection speed,which are difficult to apply in the actual wafer production process.In addition,there is a data imbalance in the wafer dataset that seriously affects the training results of the model.To reduce the complexity of the deep model without affecting the wafer feature expression,this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module.In addition,to reduce the impact of data imbalance on model training,this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer.The method proposed in this paper has an average accuracy of 95.4%on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs,and takes only 22.99 s to detect 1000 wafer pictures.Compared with the original PeleeNet network without optimization,the number of parameters and FLOPs are reduced by 92.68%and 58.85%,respectively.Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8%on the WM‐811K dataset.At the same time,the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.

An Uncertainty Analysis of Downward Pressure Applied to the Wafer Based on a Flexible Airbag by a Double Side Polishing Machine

The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer polishing,maintaining a constant pressure value applied by the polishing head is essential to achieve the desired flatness of the wafer.The accuracy of the downward pressure output by the polishing head is a crucial factor in producing flat wafers.In this paper,the uncertainty component of downward pressure is calculated and its measurement uncertainty is evaluated,and a method for calculating downward pressure uncertainty traceable to international basic unit is established.Therefore,the reliability of double side polishing machine has been significantly improved.

深硅刻蚀晶圆位置偏移分析与研究

晶圆位置偏移过大是导致深硅刻蚀设备发生传片报警问题的主要原因之一,尤其是在采用静电卡盘的设备中。阐述了晶圆位置发生偏移原因,重点研究了解吸附配方、顶针驱动和片间清洗方案。研究表明,静电吸盘的表面聚合物残留是导致静电释放不充分的主要因素,表面聚合物的清除有助于优化晶圆位置偏移。电动三针在固有残留静电力的情况下,通过缓慢连续升针方案缓解了跳片现象。优化片间清洗方案大幅减小表面聚合物残留。实验结果表明:优化后的解吸附配方为工艺时长90 s、电极功率1000 W、气压20 mTorr(1 mTorr≈0.133 Pa)、氩气体积流量250 mL/min,电动三针接触晶圆前、接触中、脱离静电吸盘后的升针速度分别为3、2和6 mm/s,在上述工艺条件下,通过进一步优化片间清洗方案,使得晶圆位置偏移量从初始的2~6 mm降至0.2 mm以内。

弹性磨抛轮加工硅片面形预测模型及试验验证

目的为分析弹性磨抛轮磨削硅片面形精度变化的影响因素,优化加工参数以获得良好的磨削面形。方法通过建立考虑弹性磨抛轮转速、硅片转速、偏心距等参数的弹性磨抛轮磨粒运动轨迹模型,结合单颗磨粒切削深度,提出了弹性磨抛轮加工硅片的材料去除非均匀性预测方法,建立了基于弹性磨抛轮磨削硅片的面形预测模型,并通过不同转速比下的磨削试验验证了预测模型的准确性。结果面形预测模型仿真出的面形与弹性磨抛轮加工试验后的硅片面形一致,均呈“凸”形,且PV值随转速比的增大而增大。转速比为1时,磨削后硅片面形PV值为0.54μm,仿真模型计算出的PV值为0.49μm,转速比为5时,磨削后硅片面形PV值为2.12μm,仿真模型计算出的PV值为2.38μm。结论磨削试验面形PV值与模型计算面形PV值的预测误差小于13%,建立的面形预测模型能够成功预测硅片的面形规律,可以分析加工参数对硅片面形的影响规律。由面形预测模型分析可知,转速比对硅片面形精度有影响,且随着转速比的增加,硅片面形不断恶化,因此在实际加工中,应选择较小的转速比进行加工,以获得更优的硅片面形精度。

双向拉伸聚乙烯薄膜专用料的结构剖析

利用凝胶渗透色谱仪(GPC)、差示扫描量热仪(DSC)和核磁共振波谱仪(NMR)等对2种进口双向拉伸聚乙烯(BOPE)薄膜专用料(SP3022和TF80)和国产茂金属线型低密度聚乙烯(mLLDPE)薄膜专用料(EZP2010HA)的结构和性能进行了分析对比。结果表明:与EZP2010HA相比,SP3022和TF80的熔体流动速率更低,相对分子质量及其分布更宽,密度、熔融温度、结晶温度、结晶度均更高,厚晶片含量更多,剪切黏度更小,更适合双向拉伸加工。

酸腐蚀工艺对硅片表面粗糙度的影响

为了缩减工艺成本,提高硅片表面光泽度,降低表面粗糙度,降低表面金属含量,提高生产效率,对HNO_(3)∶HF∶CH_(3)COOH混合酸体系的反应机理进行了分析,通过改变酸腐蚀去除量,腐蚀液温度等工艺参数可有效控制超薄硅片腐蚀反应速度,降低表面粗糙度,提高表面光泽度。发现去除量达到100μm以后,表面粗糙度可达到0.065μm,同一条件下,腐蚀液温度为45℃时,表面粗糙度最小,反射率最高。

基于微谐振器的圆片级真空封装真空度测试技术

针对微电子机械系统(MEMS)圆片级封装腔体体积小、传统的真空封装测试方法适用性差的情况,研制了一种用于表征圆片级真空封装真空度的器件——MEMS微谐振器。利用此谐振器不仅可以表征圆片级真空封装真空度,也可用于圆片级真空封装漏率的测试。采用MEMS体硅工艺和共晶圆片键合技术实现了微谐振器的圆片级真空封装,利用微谐振器阻尼特性建立了谐振器品质因数与真空度的对应关系,通过设计的激励电路实现了微谐振器品质因数的在片测试,对不同键合腔体真空度下封装的MEMS微谐振器进行测试,测试结果显示该微谐振器在高真空度0.1~8 Pa范围内品质因数与真空度有很好的对应关系。

金属钼圆基片平面研磨及其表面创成机理研究

目的实现金属钼圆基片高效平坦化加工,获得超光滑表面。方法采用游离磨料对钼圆基片进行平面研磨加工,研究磨料种类及研磨盘转速、研磨压力、研磨时间等工艺参数对研磨效果的影响规律,通过材料去除率(MRR)与表面粗糙度(Ra)的建模分析,对比钼材与高硬脆和高塑性材料,揭示其研磨工艺特性、探究其表面创成机理。结果钼圆基片材料去除快慢和表面形貌受各因素作用的综合影响。CeO_(2)磨料适合钼圆基片的研磨加工,材料去除方式为二体、三体摩擦塑性去除;在研磨过程中,MRR随研磨盘转速、研磨压力的递增而先增大后减小,在研磨盘转速为60 r/min、研磨压力为0.026 MPa条件下MRR达到最大;除磨料因素外,其他工艺因素对表面粗糙度的影响较小;MRR和Ra随加工时间的延长而趋于稳定;使用粒径W1 CeO_(2)磨料在研磨盘转速为60 r/min、研磨压力为0.026 MPa下研磨40 min后,表面粗糙度Ra由46 nm降至9.53 nm,MRR达1.16 mg/min。结论采用游离磨料研磨方法在优化工艺条件下可以有效降低表面粗糙度,获得良好表面。

基于锗激光标识的正交实验设计

为了得到标识清楚且不损伤锗晶片特性的激光标识,借助于正交实验设计的方法,对激光平均输出功率值、脉冲激光频率和标刻速度对晶片进行了DOE(正交实验设计)和极差分析。通过极差分析得到4个影响因素的主次关系为激光发生器功率值>标刻速度>激光频率>空白(其余因素)。得到标刻深度的最佳配方为标刻速度200 mm/s,激光发生器平均输出功率值46%,脉冲激光频率为18 kHz。此时标刻深度为230μm。

超临界二氧化碳介质中晶圆清洗与选择性刻蚀研究进展

随着集成电路特征尺寸的逐渐减小,器件结构会要求更高的纵横比,常规湿法清洗由于表面张力很难进入晶圆深沟槽结构内部,不能满足更细线条工艺要求和高深宽比结构,直接影响沟槽内的污染物去除效果;常规湿法刻蚀各向异性差、结构坍塌严重、深沟槽刻蚀效果不明显;而等离子体干法刻蚀则存在刻蚀速率慢、光刻胶脱落和黏附、结构损伤、废气处理等一系列问题。超临界清洗和刻蚀技术是最具有前景的环境友好、无损伤技术,能够耦合刻蚀、清洗与干燥工艺为一体,且可以循环使用,安全环保,是晶圆制造过程中常规清洗和刻蚀的首选替代技术。综述了超临界二氧化碳中晶圆清洗与选择性刻蚀的研究进展,重点介绍了超临界二氧化碳共溶剂、微乳液体系在光刻胶剥离以及含硅基底选择性蚀刻中的应用,展望了超临界二氧化碳晶圆清洗和刻蚀存在的问题和发展趋势。

碳化硅单晶加工对晶片表面质量的影响

碳化硅(4H-SiC)晶片加工是制备高品质衬底晶圆的关键工艺,衬底晶圆的表面质量直接影响外延薄膜以及后续器件的性能。本研究通过对4H-SiC晶片经线切割、磨削、研磨、抛光等不同加工工序后对应的表面形貌、粗糙度、机械性质和晶体质量的分析,发现晶片加工通过逐步去除线切割引入的表面损伤层,提高了晶片表面质量。4H-SiC晶片C面和Si面机械性质存在各向异性,C面材料韧性相对较差,加工过程中发生脆性断裂的程度更大,导致C面材料去除速率较快,表面形貌和粗糙度相对较差。

碳化硅晶圆高温磁控溅射制备铝薄膜异常结晶现象

在碳化硅表面使用高温磁控溅射法制备铝薄膜过程中有时会出现异常“斑点”现象,针对出现该异常现象可能的原因进行了研究,确认其主要因素为溅射温度和溅射功率,SiC表面状态和金属体系对异常现象的出现影响很小。采用白光干涉仪测定正常和异常区域表面形貌和粗糙度,结果表明“斑点”区域粗糙度明显低于正常区域,两者分别为1.7和5.6 nm。采用聚焦离子束分析技术对比剖面结构差异,发现“斑点”区域存在明显晶粒合并现象,金属表面晶界比正常区域少很多。“斑点”形成的可能原因是沉积过程温度过高,导致Al膜沉积初始成核过程中大量晶核合并、晶界消失,从而表面粗糙度显著降低。

基于Actor模型的众核数据流硬件架构探索

超大规模AI模型的分布式训练对芯片架构的通信能力和可扩展性提出了挑战。晶圆级芯片通过在同一片晶圆上集成大量的计算核心和互联网络,实现了超高的计算密度和通信性能,成为了训练超大规模AI模型的理想选择。AMCoDA是一种基于Actor模型的众核数据流硬件架构,旨在利用Actor并行编程模型的高度并行性、异步消息传递和高扩展性等特点,在晶圆级芯片上实现AI模型的分布式训练。AMCoDA的设计包括计算模型、执行模型和硬件架构3个层面。实验表明,AMCoDA能广泛支持分布式训练中的各种并行模式和集合通信模式,灵活高效地完成复杂分布式训练策略的部署和执行。

基于YOLOv5s的晶粒检测算法

为解决传统晶粒定位容易受到光线、噪声等因素影响,耗费大量资源等问题,构建晶粒检测算法YOLOv5s-wafer。首先建立晶粒检测数据集,使用轻量级网络GhostNetv2作为主干特征提取网络,降低模型参数量;其次在特征融合网络中引入CA(coordinate attention,CA)注意力机制,加强特征提取能力;最后采用EIOU作为定位损失函数,提高晶粒检测精度。实验结果表明:算法的平均精度均值为99.3%,参数量为4.637×10^(6),检测性能和算法轻量化达到了理想平衡。

基于遗传算法的晶圆级芯片映射算法研究

近年来,随着人工智能领域的发展,深度学习已经成为如今最重要的计算负载之一,下一代人工智能以及高性能计算应用对计算平台的算力与通信能力提出了前所未有的需求,晶圆级芯片通过在整片晶圆上集成超高密度的晶体管数量以及互连通信能力,有望为未来的人工智能与超算平台提供革命性的算力解决方案。而其中,晶圆级芯片具有的超大计算资源和独特的新架构使得任务映射算法面临前所未有的新问题,相关研究成为近年来学术界的研究重点。专注于研究人工智能任务在晶圆级硬件资源的映射算法,即通过将人工智能算法表达为多个卷积核,再考虑卷积核的算力特性来基于遗传算法设计晶圆级芯片的映射算法。一系列映射任务下的仿真结果验证了映射算法的有效性,并揭示了执行时间、适配器成本等参数对代价函数的影响。

硅片磨床伺服进给系统仿真模型与分析

在硅片磨削时,硅片加工质量与硅片磨床的进给系统性能密切相关。为了提升硅片磨床进给系统的精度和稳定性,提出了采用上位机、运动控制卡、伺服驱动器、位置传感器进行闭环控制进给的技术方案。研究了伺服系统和机械系统两者之间的相互耦合关系,建立了动力学模型,搭建了基于PID控制的三闭环控制系统,采用MATLAB中Simulink模块对进给系统进行仿真分析。仿真结果表明,磨床进给系统速度波动量在1%以下满足硅片磨削对进给精度的要求。