The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling （VMS） scheme while the current-mode signaling （CMS） scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and A B CD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by A B CD parameter matrix approach are in good accordance with the simulation results of the advanced design system.

A Multiple-Valued Algebra for Modeling MOS VLSI Circuits at Switch-Level

A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper. Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a switch-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

SOME COMBINATORIAL OPTIMIZATION PROBLEMS ARISING FROM VLSI CIRCUIT DESIGN

This paper is basically a survey to show a number of combinatorial optimization problems arising from VLSI circuit design. Some of them including the existence problem, minimax problem, net representation, bend minimization, area minimization, placement problem, routing problem, etc. are especially discussed with new results and theoretical ideas for treating them. Finally, a number of problems for further research are mentioned.

Modified Multi-Resolution Telescopic Search Algorithm for Block-Matching Motion Estimation

This paper presents a modified multi-resolution telescopic search algorithm (MRTlcSA) for the block-matching motion estimation. A novel inverse telescopic search is substituted for the conventional telescopic search, that reduces the on-chip memory size and memory bandwidth for VLSI implementation. In addition, strategies of motion track and adaptive search window are applied to reduce the computational complexity of motion estimation. Simulation results show that, compared with the MRTleSA, the proposed algorithm reduces the computational load to only 30% while preserving almost the same image quality. Comparisons on hardware cost and power consumption of the VLSI implementations using the two algorithms are also presented in the paper.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

Test Vector Optimization Using Pocofan-Poframe Partitionin

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

A minimum-order boundary element method to extract the 3-D inductance and resistance of the interconnects in VLSI

The high frequency resistance and inductance of the 3-D complex interconnect structures can be calculated by solving an eddy current electromagnetic problem. In this paper, a model for charactering such a 3-D eddy current problem is proposed, in which the electromagnetic fields in both the conducting and non-conducting regions are described in terms of the magnetic vector potential, and a set of the indirect boundary integral equations (IBIE) is obtained. The IBIEs can be solved by boundary element method, so this method avoids discretizing the domain of the conductors. As an indirect boundary element method, it is of minimum order. It does not restrict the direction of the current in conductors, and hence it can consider the mutual impedance between two perpendicular conductors. The numerical results can well meet the analytical solution of a 2-D problem. The mutual impedance of two perpendicular conductors is also shown under the different gaps between conductors and different frequencies.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Repairing VLSI/WSI Redundant Memories with Minimum Cost

A new approach to repair memory chips with redundancy is proposed.This approach is based on the minimization of the repair cost.Algorithms for cost driven repair are presented.The algorithms can be ex- ecuted either on-line(concurrently with the testing of the memory),or off-line(at completion of testing). Analytical expressions for the repair cost under both circumstances are given.The presented algorithms are also perfect in the sense that they can correctly diagnose a repairable/unrepairable memory and find the optimal repair-solution.