Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Fi...Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.展开更多
This article describes the prototype of the read-out subsystem which will be subject to the BESIII data acquisition system. According to the purpose of the BESIII, the event rate will be about 4000 Hz and the data rat...This article describes the prototype of the read-out subsystem which will be subject to the BESIII data acquisition system. According to the purpose of the BESIII, the event rate will be about 4000 Hz and the data rate up to 50 Mbytes/sec after Level 1 trigger. The read-out subsystem consists of some read-out crates and a read-out computer whose function is to initialize the hardware, to collect the event data from the front-end electronics after Level 1 trigger, to transfer data fragments to the computer in online form through two levels of computer pre-processing and high-speed network transmission. In this model, the crate level read-out implementation is based on the commercial single board computer MVME5100 running the VxWorks operating system. The article outlines the structure of the crate level testing platform of hardware and software. It puts emphasis on the framework of the read-out test model, data process flow and test method at crate level. Especially, it enumerates the key technologies in the process of design and analyses the test results. In addition, results which summarize the performance of the single board computer from the data transferring aspects will be presented.展开更多
文摘Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.
基金The project supported by Beijing Electron Positron Collider (BEPCII) Upgrade Project
文摘This article describes the prototype of the read-out subsystem which will be subject to the BESIII data acquisition system. According to the purpose of the BESIII, the event rate will be about 4000 Hz and the data rate up to 50 Mbytes/sec after Level 1 trigger. The read-out subsystem consists of some read-out crates and a read-out computer whose function is to initialize the hardware, to collect the event data from the front-end electronics after Level 1 trigger, to transfer data fragments to the computer in online form through two levels of computer pre-processing and high-speed network transmission. In this model, the crate level read-out implementation is based on the commercial single board computer MVME5100 running the VxWorks operating system. The article outlines the structure of the crate level testing platform of hardware and software. It puts emphasis on the framework of the read-out test model, data process flow and test method at crate level. Especially, it enumerates the key technologies in the process of design and analyses the test results. In addition, results which summarize the performance of the single board computer from the data transferring aspects will be presented.
