一种基于电容中和技术的低功耗宽带VGA设计

阐述一种基于电容中和技术的宽带可变增益放大器(VGA),用于高速通信和高分辨率雷达系统。提出的负电容通路有效地拓展了带宽,并在不同的增益设定下实现平坦的带内增益。仿真结果表明,VGA在增益-2.8~49.4dB调节范围内均实现带宽超过4.0GHz。它的功耗在1V的电源电压下为16.5mW,核心电路面积为0.006 mm^(2)。

A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier(VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended by using cascode architecture together with active inductive load. To achieve small parasitic and low area,direct current(DC) coupling is adopted in the circuit while a DC offset cancellation(DCOC) circuit is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process, the chip occupies an area of 0.53 mm×0.48 mm(including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from-40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage（all gains）.Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier（VG-LNA） for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA＇s input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB（-3.3 dB to 21.7 dB） variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier （VGA） and a power amplifier （PA） driver are designed for WLAN IEEE 802.11 a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12 × 1.25 mm^2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point （OIP3） of 11 dBm. The gain drift over the temperature varying from -30 to 85 ℃ converges within ±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

一种适用于生物医学信号采集的高线性度VGA

传统VGA线性度较低,不适用于生物医学应用。文章分析了基于可编程跨导器的传统结构,得出环路增益和失真的关系,并基于此采用增益提升技术提高环路增益,设计了一种新型的基于可编程跨导器的VGA,提高了VGA的线性度。仿真结果表明,在1.2 V电源电压下,电路消耗电流为10μA,在0~30 mV的输入信号幅度范围内,VGA的总谐波失真不高于0.5%,IM3减小14 dB,IIP3为18.57 dBm,在0.1 Hz~100 kHz范围内,等效输入噪声为616 nV。

一种用于5G终端增益可调的低噪声放大器设计

针对无线接收机需要对不同强度信号进行不同程度放大的要求,采用WIN公司的0.15μm GaAs pHEMT工艺设计了一款工作频段为5G通信频段3~5 GHz的可变增益低噪声放大器。该放大器包含两级放大电路,均采用自偏置结构,降低了端口数量,通过调节第二级放大电路的控制电压在0至5 V之间变化,可实现系统增益的连续可调范围约39.3 dB(-3.5~35.8 dB)。放大器版图尺寸为0.94×1.24 mm^(2)。控制电压为0 V时,系统噪声为0.53±0.01 dB,增益为35.5±0.35 dB,中心频点4 GHz处,OP1dB为13.2 dBm, OIP3达到32.7 dBm,表明系统具有良好的线性度。

一种基于T型伪电阻的可调超低高通角VGA

为了对超低频率的生物医学信号进行有效地调节和放大,提出了一种应用于VGA直流偏置电路的阻值可调的T型伪电阻网络,其超大的等效电阻与反馈电容形成的RC高通滤波环路可构成VGA的超低高通角。电路采用SMIC 0.18μm CMOS工艺进行设计和验证,后仿真结果表明,其高通角调节范围为0.16~410.8mHz,增益以3dB步长从10~49dB变化,等效输入噪声达2.7μV（rms）,总谐波失真（THD）仅为0.30%,具有高通角频率超低且可调、输入噪声低和THD低等特点,适用于高精度的人体心电信号采集等生物医学系统。

Ka波段CMOS有源矢量合成移相器

本文基于65 nm硅基互补金属氧化物半导体工艺设计了一款Ka波段有源矢量合成移相器。该电路由正交耦合器、单端转差分信号的巴伦、可变增益放大器、信号合成网络组成。基于集总LC等效模型的正交发生器能够实现紧凑尺寸并获得高精度正交信号;可变增益放大器采用数字控制的共源共栅架构,能够实现精准的幅度调节,并提高输入输出之间的隔离度。实测结果表明,该移相器可在25 GHz~32 GHz频带范围内实现360°移相,相位步进5.625°,均方根(RMS)相位误差小于3°,寄生调幅RMS小于1 dB,电路面积为800μm×400μm,功耗11 mW。

高性能可变增益放大器(VGA)设计探讨

可变增益放大器（VGA）是模拟电路的一个基本组成模块。它们已经在移动通信系统,硬盘驱动系统等领域得到了广泛的应用。随着深亚微米CMOS工艺的到来,集成电路的特征尺寸越来越小,电源电压逐渐降低,高性能的VGA设计向模拟电路设计师提出了严峻的挑战。鉴于此,探讨了一些高性能VGA的设计技术,对开环VGA和闭环VGA两种结构作了详细的论述,并分析了相应的增益控制方法和优缺点。最后介绍了一种用于低压低功耗设计的高性能VGA增益级电路结构,并提出了VGA各种性能参数之间的折衷设计。

一种输出电压可编程的闭环CMOS VGA的设计

利用SMIC0.18μmCOMS混合工艺,针对无线通信系统中的信号接收机,设计了一个能够工作在40MHz频带内的中频闭环可变增益放大器VGA,它包括可编程的输出电压和数字化的自动增益控制AGC电路。可编程的输出电压使得该VGA能够很好的适应不同应用方案下的动态范围要求;通常情况下,AGC电路依靠DSP基带芯片实现,然而,这里重点讨论从DSP芯片分离出来的数字AGC电路,独立的AGC电路使得VGA和DSP可以各自集中精力于自己的工作,降低部件相关性。该闭环VGA具有20dB增益调整范围,可编程输出AC电压峰峰值Vp-p能够以每50mV为一档从100mV编程到300mV。

下截止频率1.3～244 Hz可调带通VGA设计

采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节。提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围。将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题。该VGA电路采用TSMC 0.18μm标准工艺设计和流片,测试结果表明,1.2 V电源电压下,其下截止频率调节范围为1.3~244 Hz,增益为49.2,44.2,39.2 d B,带宽为3.4,3.9,4.4 k Hz,消耗电流为3.9μA,共模抑制比达75.2 d B。

应用于GPS接收机的宽动态范围连续VGA

针对全球定位系统(GPS)接收机中宽动态范围的要求,提出了一种伪指数近似可变增益放大器(VGA)。该VGA在改进的吉尔伯特单元基础上,采用电压-电流转换电路构成伪指数函数,通过两级级联方式来实现宽线性增益范围,且电路结构对温度不敏感。测试结果表明,当控制电压在0.41.45V变化时,该VGA的线性增益范围为2080dB。在50dB线性增益范围内,增益随温度变化的最大偏差不大于±1.5dB。

用于数字电视调谐芯片的高线性CMOS VGA

设计了一种适于DVB-C标准的中频可变增益放大器。该放大器由三部分构成:电流调节型可变增益单元、基于差分对管传输特性的指数控制电压产生电路以及一高线性输出级。采用Chartered0.25μm RFCMOS工艺库下流片。测试结果表明,4～49dB的连续增益范围,100MHz的3dB带宽,50Ω负载下的OIP3为16.8dBm。

CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control(AGC) circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier(VGA) chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 μm standard CMOS process. Simulation and measurement results verified that its gain ranged from-20 dB to 30 dB, and bandwidth ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

用于宽带任意波发生器的可变增益放大器

在宽带任意波发生器(AWG)研制中,一个重要的挑战来自宽带可变增益放大器(VGA)。作为设备的信号输出接口电路,VGA承担了输出信号放大、共模电压调节、驱动负载等重要功能,在很大程度上决定了设备的综合性能。设计了一款适用于宽带AWG的VGA芯片,采用一种改进的数字增益调节架构,在兼顾带宽的同时,消除了模拟控制电压的影响,并确保了增益的单调性。芯片采用SiGe BiCMOS工艺实现,测试结果表明,芯片可以实现0.125~2倍的单调增益控制,最小增益步进约为0.125倍;在输入信号频率为4 GHz时的输出信号衰减为-2.83 d B。

高精度可变增益放大器的研究与设计

为了实现可变增益放大器高精度及大动态范围的优势,基于GaAs 0.25μm pHEMT工艺,设计了一款工作在0.1~4.0 GHz并行控制的可变增益放大器。放大器由数控衰减器和射频放大器组成。数控衰减单元采用桥T型结构和电平转换电路来实现;正压控制衰减电路简化了电路结构,提高电路可靠性;改进型并联电容补偿衰减结构改善大衰减态高频衰减精度;射频放大器电路采用并联电阻负反馈的共源共栅(Cascode)结构,实现了高增益平坦度和大动态范围。测试结果显示,在工作频带内,可变增益放大器的增益可达20 dB以上、平坦度在1.5 dB以内,可变增益范围为0~31.5 dB、衰减步进0.5 dB,输出三阶交调点最高可达39 dBm,端口回波损耗均小于-15 dB。

一款3~6.3 GHz增益可调的低噪声放大器设计

针对无线接收机在对不同信号进行放大时,噪声恶化严重的问题,文中在驱动放大级采用电流复用技术,可以降低系统功耗,同时,在增益变化过程中保证了输入级增益对后级电路噪声的抑制作用,使得增益变化过程中,噪声始终低于1 dB。输入级和输出级阻抗匹配良好,在3 GHz~6.3 GHz的工作频段上可实现系统增益的连续可调范围约30 dB(19.6 dB~49.6 dB),同时通过采用两个控制电压分别控制两级放大电路,在增益变化过程中系统获得了良好的增益平坦度,版图尺寸为0.95×1.53 mm^(2)。在常规工作状态下,系统噪声为0.56±0.02 dB,增益为49.6±0.47 dB,功耗97 mW。在4.5 GHz频率处,系统的OP1dB为10.3 dBm,OIP3达到29 dBm,具有良好的线性度。

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier （LNA） is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S（1, 1） less than -9 dB and S（2, 2） less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point （IIP3） is -2 dBm.