Characterization of FEEWAVE,a low‑power waveform digitizer ASIC with 15‑ps time resolution

Purpose FEEWAVE is a chip with a waveform digitizer based on a switched capacitor array(SCA).A SCA uses capacitor arrays to store waveforms and exhibits low-power consumption and high time resolution performance.However,the limitations of the chip manufacturing process induce sampling interval and digitization deviations between different cells,which affects the performance of the chip.Methods Calibration was performed on the SCA sampling part on the FEEWAVE chip to obtain more accurate digitized output and time intervals between the sampling cells.Experiments were carried out according to the proposed amplitude and time calibration methods,and the time resolution of the chip was further improved by a fitting algorithm.Results and conclusion Through the calibration algorithm,the time resolution of the SCA sampling part of the chip reached 9.0 ps after calibration.In the self-test of the electronics time performance,the time measurement after leading-edge fitting and calibration was approximately 12.3 ps.In the joint test with silicon photomultiplier detectors,the time resolution of the SCA part was low and comparable to the resolution of the oscilloscope after calibration algorithm and waveform fitting.

A high time resolution and low-power ASIC for MRPC applications

Purpose The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber(MRPC)in Beijing SpectrometerⅢexperiments,posing a demand for the high time resolution and low-power electronics.Methods Considering MRPC features,an application-specific integrated circuit(ASIC)called FEEWAVE,which integrates the front-end circuit and digitization function,is proposed to meet the above requirements.The front-end circuit implements I/V conversion and signal amplification.To reduce power consumption and further improve the time resolution,the waveform sampling technique based on switch capacitor array is adopted.Results and conclusion A 30 fC to 1.2 pC input signal dynamic range is obtained,and the jitter is less than 21 ps rms.At the same time,the chip realizes 5 GSPS(gigabit samples per second)sampling rate,trigger rate capability of 50 kHz and 25 mW/channel power consumption.The 6-channel ASIC has been designed and taped out with 0.18μm complementary metal oxide semiconductor technology.The preliminary test results of FEEWAVE have been achieved.