Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed ...Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed algorithm has been implemented with C language. Fourteen Mi- croelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.展开更多
To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an op...To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.展开更多
In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In fir...In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] μW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] μW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] μW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] μW. Simulations have been performed by using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.展开更多
n变量的逻辑函数具有2n个固定极性,而每个极性对应不同的DFRM(Dual Forms of Reed-Muller)逻辑展开式,因此极性直接影响着DFRM电路的面积和功耗。通过对DFRM逻辑展开式和极性转换算法的研究,本文成功地将遗传算法应用于DFRM逻辑电路最...n变量的逻辑函数具有2n个固定极性,而每个极性对应不同的DFRM(Dual Forms of Reed-Muller)逻辑展开式,因此极性直接影响着DFRM电路的面积和功耗。通过对DFRM逻辑展开式和极性转换算法的研究,本文成功地将遗传算法应用于DFRM逻辑电路最佳极性的搜索。对10个较大规模的MCNC Benchmark电路测试表明,所提算法搜索到的最佳极性相对应的DFRM电路,与极性0时的DFRM电路相比,面积和功耗的平均节省分别达到了75.0%和65.2%。展开更多
基金Supported by the National Natural Science Foundation of China (No.60776022)the Science and Technology Fund of Zhejiang Province (No.2008C21166)+2 种基金the Scientific Re-search Fund of Zhejiang Provincial Education Department (No.20070859)the Natural Science Fundation of Ningbo (No.2008A610005)the Professor or Doctor Fund of Ningbo University
文摘Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed algorithm has been implemented with C language. Fourteen Mi- croelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.
文摘To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.
文摘In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] μW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] μW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] μW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] μW. Simulations have been performed by using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.
文摘n变量的逻辑函数具有2n个固定极性,而每个极性对应不同的DFRM(Dual Forms of Reed-Muller)逻辑展开式,因此极性直接影响着DFRM电路的面积和功耗。通过对DFRM逻辑展开式和极性转换算法的研究,本文成功地将遗传算法应用于DFRM逻辑电路最佳极性的搜索。对10个较大规模的MCNC Benchmark电路测试表明,所提算法搜索到的最佳极性相对应的DFRM电路,与极性0时的DFRM电路相比,面积和功耗的平均节省分别达到了75.0%和65.2%。
